Marseille Networks, based out of Silicon Valley, CA is claiming a lot with their latest press release, but only partially reveals its hand. The company claims to have reinvented the fabless semiconductor development process through what it refers to as a virtual tape-out methodology. These claims become even more stunning, when one considers that, as pointed out by VentureBeat’s Dean Takahashi, the company has a mere 20 employees and has raised a paltry, by semiconductor startup standards, $5 million in funding. Claims like these could be easily dismissed as wishful thinking on part of the company’s founders, but Marseille’s introduction of a complete line of Quad-HD (2160p – 3840 x 2160) video processors for the flat-panel TV, PC, and A/V markets makes this a bit difficult. Especially, since the company maintains that these complex chips were developed in less than 12 months. As part of the company’s Video Through Virtualization (VTV) 1200 family of processor, these chips have native Quad-HD support and also perform up-scaling of legacy HD content to Quad-HD. From the company’s press release it is not clear if a demo utilizing these new processors was performed at CES this year. Maybe someone who stopped by Marseille’s booth at CES could comment on this?

And while specifications and block diagrams are available for the VTV-1200 family of processors on Marseille’s website and are generally self-explanatory, how exactly the virtual tape-out methodology works is significantly less clear. According to the company, the VTV platform which enables the virtual tape-out flow is a hybrid hardware emulation and software simulation environment which sits on-top of Marseille’s proprietary switch fabric. The VTV platform consists of four major components: Tools, Hardware, Libraries, and Methodology. The info on the company’s web-site seems to indicate that the hardware is FPGA based. The key benefit, as shown in the picture above, seems to stem from the customer’s ability to start developing their software before the final chip is delivered, which in turn the company suggest should save anywhere between 6 – 12 months in design time. Based on this I fail to see how this is really a reinvention of the fabless development process. There are plenty of companies in the chip industry that provide software based simulators and FPGA based emulators to customers way before they deliver the final silicon. Of course, there might be more to the virtual tape-out flow than might appear at first. Are customers allowed to modify the architecture, integrate custom IP, and then re-program the FPGA continuously to analyze the changes in performance? Are the changes then communicated back to Marseille’s to be integrated into the final IC? Maybe, but as stated before, it is not exactly clear from the information that Marseille’s has published so far.