Having covered magnetoresistive random access memory (MRAM) on several occasions it is time to move on to something a little bit more exotic, namely nanotubes. The January issue of the Nature Nanotechnology Magazine contains a very interesting article titled: Nanoscale Memory Cell based on a Nanoelectromechanical Switched Capacitor. Unfortunately, unless you are a subscriber to the magazine or might have access to it through your company, you will not be able to access the full article. Thankfully, nanowerk.com has a pretty nice write-up on the article and even obtained permission to reprint several of the illustrations. Looking at these illustrations, it can be seen that the proposed device is a three terminal device consisting of a source, drain, and gate. The source and drain both contain vertical multiwalled carbon nanotubes (MWCNT). The nanotube on the source, which is grounded, is covered with a dielectric layer which in turn is covered with a metal layer, thus completing the capacitor. The drain terminal is connected to what in a conventional design would be a bit-line and the gate terminal is connected to what would be a word-line. The mechanical switching occurs when bias voltages are applied to the drain and gate terminals. That is, when a gate voltage is applied but no drain voltage is applied, nothing happens. However, when both drain and gate voltages are applied, such that the gate voltage is higher than the drain voltage, the nanotube on the drain is subject to a repulsive electrostatic force from the gate and bends towards the source. If it bends far enough it establishes contact with the metal layer of the source and charges the capacitor effectively storing a logical one in the bit-cell, hence the name nanoelectromechanical switched capacitor (NEM).

The authors of this paper have only implemented the writing portion so far, but according to the paper, reading from the bit-cell would follow a similar sequence with the exception that the nanotube on the drain would be unable to make contact with a bit-cell that contained a logical one since even though it would still experience an electrostatic force from the gate, it would also be subject to a counter force from the charged capacitor, and thus no current would flow from the capacitor to any current sensing circuitry. All of the above is just a brief summary, the article contains all the dimensions used for constructing the device, a detailed description of the manufacturing method, all the voltages and capacitance numbers, and of course a few equations for calculating the switching speeds and effective capacitances, and is therefore definitely worth a look if you have access to it. While all of this is very preliminary work, it is nevertheless very fascinating and only gives us a small glimpse of all the esoteric structures that circuit designers might get to play with in the coming years.

Shocking Technologies Inc. has to be one of the more unique names for a company in the semiconductor field. At first, one might assume justly that they might be working on a product to compete with the Taser, but in actuality quite the contrary is the case. Shocking Technologies is currently developing voltage switchable dielectric materials which are targeted at the printed circuit board (PCB) and semiconductor packaging markets to prevent electrostatic discharge events. As far as the name is concerned maybe it is supposed to imply that this new technology is going to prevent shocking to electronic components – but that might be a stretch.

Shocking Technologies is based out of San Jose California, and in April of last year raised $7M in first round funding from ARCH Venture Partners and ATA Ventures. More recently the company raised an additional $4M in venture debt from Hercules Technology Growth Capital in late December. Surprisingly, finding additional information about the company is rather difficult since their own web site only contains a brief introductory paragraph followed by contact information. Digging around the web one can find that the company’s CEO is Lex Kosowsky who has previously held positions at DMS Technologies, Leading Technologies, and National Semiconductor, but technical information is harder to come by. The only thing available is a single US Patent #6797145 that was issued to the company’s CEO in 2004. Like most patents it is a rather lengthy and not exactly easily readable document, but the general idea is this: Above a characteristic voltage the dielectric material switches from being a dielectric to a conductive material and thus creates an alternative path for the excessive current and hence protects other electronic components. There definitely is a market for this technology, so we’ll be keeping an eye on Shocking Technologies and Lex to see whether they can deliver what they claim in the patent.

Back in December I wrote a short post about magnetoresistive random access memory (MRAM), and a few competing technologies, as well as a short mention about Freescale’s current efforts. Given MRAM’s potential it should be of no surprise that Freescale is not the only name in town when it comes to MRAM. Micromem Technologies Inc., a Canadian fabless semiconductor device company based out of Toronto, announced the other week that they have manufactured a foundry grade fully functional MRAM cell, and intend to deliver it packaged for testing later this month. The company is currently proceeding with a test plan for a 64bit MRAM that builds on top of the current MRAM cell. The 64bit MRAM arrays are expected to be available for testing in three to four months. The currently produced MRAM cell is implemented in a Gallium Arsenide process, but the company intends to migrate its technology into to Silicon Germanium process as well to satisfy the lower cost, higher density memory market. Performance numbers for Micromem’s MRAM are currently no available, but the company expects to communicate the performance data in early February. Capacity wise Micromem is currently far behind players like Freescale who offer chips with up to 4Mbit capacity, but the company claims that its products are significantly less complex, and will be cheaper and less problem prone than competing products. The reduced complexity stems from the fact that Micromem is not utilizing the magnetic tunnel junction (MTJ) approach selected by many of its competitors, which introduces tunnel barrier and structural complexity, but instead opts for using a Hall Cross-Sensor (HCS) approach, thus the name HCS MRAM. Below is a diagram depicting the HCS device concept taken from the Micromem’s press release describing their successful HCS test. Micromem is initially targeting radiation hard applications, radar systems, satellites and sensors with their technology. Overall the technology seems promising; however, it is hard to make a call without any performance numbers so that it can be compared to other MRAM implementation. And while the company has successfully implemented a single bit, it will be interesting to see how their technology scales to larger arrays, and whether the HCS approach will really yield cheaper and more reliable MRAMs than the MTJ approach.