Earlier this week, WiSpry received an additional $7 million of Series B funding, brining the company’s total funding to $18 million so far. Based out of Irvine, California, WiSpry is a fabless semiconductor startup focused on the mobile communications market. In particular, the company has developed programmable radio frequency (RF) products which are made possible through the company’s patented integration technique of micro-electro-magnetic-systems (MEMS) devices with typical industry RF-CMOS flows. This in turn enables MEMS to be manufactured in regular IC foundries rather than in specific MEMS foundries as is done typically. For those not familiar with this technology, MEMS are microscopic devices that utilize moving parts to accomplish mechanical actions. Many companies utilize MEMS in their products, for example, TI the largest MEMS manufacturer in 2006 utilized them in their DLP chips, while Canon and HP utilized them in their printers. The real benefit of WiSpry’s approach is that it enables really tight integration of micro-electronics with micro-mechanical devices, effectively enabling complete system-on-a-chip solutions. According to the company, their process can be integrated with active silicon and is process agnostic, thus able to work with CMOS, SiGe, BiCMOS and GaAs. Currently, WiSpry’s product line is a family of RF-MEMS tunable digital capacitors that are offered in networked configurations. These capacitors operate similarly to regular parallel-plate capacitors, however the distance between the plates is tunable due to MEMS technology, and as such the capacitance can be varied. This product line is initially targeted at wireless devices for antenna tuning and filter applications. Further down the line WiSpry envisions the integration of their technology into transceivers, low-noise amplifiers and power amplifiers. The important part here is for the integration of the MEMS not to slow-down the production of the rest of the ICs significantly, or else it might become more cost effective for companies to do the production of these two separately. However, if this challenge can be overcome and given the fact that the market for wireless devices which require ever tighter integration of components is still growing, the market opportunities for WiSpry seem lucrative.

Memory capacity is one of those things that developers seem to have an infinite appetite for. How programs worked in the old days with a few Kbytes of memory is almost a mystery, but then again the type of information that is being crammed into memory for the sake of performance today is significantly different than even a decades ago. Yet, one has to wonder if programmers have gotten a ted lazy after trading in assembly skills for compiler optimizations. Regardless, MetaRAM, a two year old startup out of San Jose, California that emerged from stealth-mode a week ago is poised to make many new friends with their recent announcement of being able to quadruple the DRAM capacity of existing systems using existing DIMMs. Backed by several prominent venture capital firms including Kleiner Perkins Caulfield & Byers, Khosla Ventures, Storm Ventures, and Intel Capital, and led by Fred Weber who led the development of the Opteron processor at AMD, MetaRAM developed what they call MetaSDRAM technology.

As shown above, MetaRAM’s trick is a chipset that sits between the system memory controller and the actual DRAM. This chipset, which consists of an access manager chip, either the AM150 or AM160, and several flow controller chips, FC540, enables support for up to 16GB DIMMs without the need for any other hardware or software changes within the system. These chips work in tandem at speeds of up to 667 MT/s while being transparent to the host memory controller as well as the DRAMs.  This is definitely a clever trick, and as long as it does not inhibit the operating frequency it is a great way for upgrading current systems without having to re-work any additional hardware. Two questions emerge however that the company will have to address in the future: First, as the operating frequency of DRAMs increases, how long will MetaRAM be able to hide the latency of their chipset via clever buffering of reads and writes? Second, it is inevitable that memory controllers in the future will enable support for ever larger amounts of memory, is it possible therefore that at some point the amount of memory on a memory module will simply be limited by the physical integration limit, rather than by the controller capability? But for now things seem to be well at MetaRAM; several vendors have announced products based on MetaRAM’s chipsets and the company has also several open positions for those looking for something new to work on. If you want to find out a little bit more about the company’s co-founder and CEO head on over to The Register, where you can find a very interesting interview with Fred Weber which covers his career from the early days at Harvard, through NextGen, AMD, and finally MetaRAM.

On the mobile side of things Intel presented a processor targeted at ultra mobile applications capable of running at up to 2GHz - not bad for a sub 2W part. Intel highlighted the fact that their power analysis showed that a simple in-order multi-threaded machine was the best option for low-power applications. Additionally, the core also featured a special array for processor state preservation while the core was in sleep mode, thus allowing for quick wake-up times. Not to be outdone, TI presented an SOC that had everything but kitchen-sink on it, including an ARM core, a DSP chip, and an imager processor. The TI core utilized extensive body-biasing including forward body -biasing for cold-devices and reverse body-biasing for hot deices. The biasing was combined with specific power-states to obtain maximum performance or power savings.

The SRAM session also featured several interesting papers and once again body-biasing was used extensively. Intel, in addition to an op-amp based active feedback sleep scheme, utilized forward body-biasing on pmos devices in their 6T bit-cells to improve low-voltage operation of their arrays. Renesas on the other hand utilized reverse body-biasing on their nmos and pmos devices in conjunction with threshold monitoring to reduce mismatch between devices and thus improving the operating margins of their SRAMs. IBM presented a two-stage sense amplifier that significantly reduced power since it reduced the voltage swing on their global data lines. Their array also featured an embedded trench capacitor which stores enough charge to allow the array to exit from retention-mode with no cycle penalty. Kawasaki presented an asymmetric 6T cell, which featured very good static noise margin and write margin numbers - their numbers seemed almost too good to be true, but the presenter argued that the larger devices compensated for the asymmetric distortion. MIT presented a quite interesting single-ended non-strobed sense-amp (NSR-SA), which seems to have better mean and sigma variation than conventional differential sense-amplifiers. It requires several ratioed circuits and also incurs a power penalty due to crowbar currents, but is interesting nevertheless. Finally, just like every year a 10T sub-threshold bit-cell was presented for ultra low-power designs, this year by Purdue and IBM.