Once in a while you run across an interesting web-site, that while probably not of too much use to those who are deeply familiar with a particular field, might be of quite some use to those in adjacent and related fields. Let’s face it, for most design engineers it is very difficult not to get pigeonholed. That is, we are very familiar with the particular tools that are required for us to perform our daily job, but our knowledge of tools that another horizontal group in the organization might be using is very limited. It becomes even worse when one works for a company that mostly utilizes internal tools, for then you might become completely oblivious to what external tools in your field of practice might be capable of. Even if you make the effort to learn about some of the external offerings, you might get as far as the big three (Cadence, Synopsys, and Mentor), and have no idea about all the startups that are working on new and innovative tools. Well, as it turns out if you are interested in electronic design automation (EDA), you might be in luck, for there exists a website called Demos On Demand, that features a generous amount of videos from a myriad of EDA vendors.

The presentations are organized into several high-level categories such as front-end, back-end, low-power, manufacturing and so one. Under each of these categories one can find further sub-categories to ease the search process for videos of interest. The site also features interviews with what it labels as experts, which most of the time turn out to be the founders of particular companies. It features a few training tutorials, however these are very limited, so one is probably better off going to a particular company’s website for help and tutorials. The seminar selection is nominally better, although a few more would not hurt. From the startup perspective, the most interesting section is hands down the featured startup section under featured content. There, one can find a list of descriptions and videos for 25 or so startups in the EDA field. Now, I’m no EDA expert, but several of the companies on the list have been acquired by now, so it might be that the site’s content might be a little dated. Also, don’t expect any in-depth content in the videos; they are more or less technical marketing sales presentations for a company’s product. One annoying thing is that one needs to login to view the full video content. Creating an account in itself would not be much of an issue if the account creation worked properly that is. I had serious issues logging-in after creating my account. Nevertheless, as a springboard for finding out about some of the EDA startups out there this site is a decent start.

There are so many interesting conferences, symposia, and panel discussions that it is pity that one cannot attend them all. As such, it is always nice when someone who does attend an interesting event, takes the time to post of few highlight. Even better when a nice succinct trip report with some observations and commentary is provided. This time, the thanks go out to Mike Demler, and his The World is Analog blog for providing excellent coverage from the 10th Annual Wireless Communications Alliance (WCA) What’s Hot and What’s Not in Mobility 2009 investor panel discussion that occurred last week in Santa Clara, CA. Part 1 of the report can be found here, and part two can be found here. The panel consisted of Eric Zimits (Managing Director, Granite Ventures), Dev Khare (Vice President, Venrock), Tim Chang (Principal, Nortwest Venture Partners, and Scott Raney (Partner, Redpoint Ventures), and was moderated by Scott Ellison (VP Mobility Wireless, IDC). I encourage you to take some time and read both parts as they contain some interesting highlights and observations on a variety of subjects including: venture capital, mobile - software, services, infrastructure, TV, health, commerce, and advertising - just to mention a few.

If you are only interested in semiconductor startup related comments, here are the key takeaways: Startup capital for fabless digital design startups is almost non-existent. And while that Panelists placed the blame on China’s plethora of fabless design startups, I’m more in agreement with Mike’s observation that it is the cost of developing chips on the leading edge process that has erased the value proposition for potential investors. The Panelists were in agreement on the fact that RF and analog areas where a much better opportunity for semiconductor startups mostly due the smaller team sizes that are needed. The number of RF and mixed-signal startups that we have covered on this blog over the last few months very much supports this notion. As a matter of fact, I would say that any startup that can take what is usually considered an analog design problem and can find a digital implementation for it stands a good chance of finding some funding especially in the wireless space. On a related note, Femtocells are also becoming increasingly of interest mostly due to the bandwidth overloading that is currently experienced by the majority of the wireless carriers. We covered a startup called Percello last year that specializes in basebend processors for the Femtocell market. Finally, on the mobile processor side of things, the panelists held a strong believe that ARM will eat Intel’s lunch over the next few years and displace Intel’s Atom processor in the netbook/smartbook and smartphone markets. Once again I have to agree with Mike that one should never underestimate Intel, even if they are a relative newcomer to the SoC space (disclosure: I do have an affiliation with Intel; however, the opinions on this blog are purely and completely mine, and are not reflective of Intel’s opinions and business strategy).

Every time semiconductor companies move to the next process node one thing is for sure, the variability of small devices will likely increase once again, much to the dismay of circuit designers. These same circuit designers will then go off and perform a myriad of simulations to figure out how to size all the gates in the design in order to mitigate the increased variability, and thus reduces its yield impact. Well, not matter how hard the process and design engineers try; there will always be some variability from chip to chip, die to die, waver to waver, and so on. As it turns out, there might be a hidden benefit in this variability that when utilized properly can be used as an identification feature to ensure that the purchased product is a genuine one. Enter Verayo, a semiconductor startup out of San Jose, CA currently developing Physical Unclonable Functions (PUF) technology. For a detailed overview of Verayo I encourage you to read this VentureBeat article by Dean Takahashi, and for a little technical dicussion continue right along here. Below is graphic that depicts a quick overview of the general idea:

Essentially, the PUF technology is a circuit that is implemented onto the chip itself. This circuit, when exposed to an input vector produces a unique output vector, which can then be utilized to uniquely identify the chip. When the chip needs to be identified, an input vector is supplied and compared against a database of correct answers for that serial number. Since each chip varies ever so slightly from the next one, this circuit essentially utilizes this variation to create a unique electronic fingerprint for each device. In a similar manner, Verayo has developed what it calls a CryptoPUF, which exploits chip variation to generate unique secret keys for each IC, thus preventing the ICs from having to store these keys somewhere in memory which makes them vulnerable to hacking.

I have to admit I would be profoundly interested in seeing the actual circuit that Verayo has developed to generate these output vectors given an input sequence. It seems to me that this circuit has two very contradictory requirements. On the one hand, it must be sensitive enough, so that when two chips vary only slightly it can still generate unique output sequences for both of them. On the other hand, it must be robust enough to reliably generate the same output given a specific input. And it must be able to do this over a wide range of atmospheric conditions. This patent application, filed by Verayo in September of last year, is probably as much information as we can expect to obtain for now. Essentially, it describes a similar circuit as shown above, consisting of two parallel delays paths mostly made up of muxes that are controlled by the input vector. The output of these two paths is then combined using an XOR gate, to create a single output bit result. Well, things are not quite that simple, the patent also throws in some possible sequencers and hash elements to make things just a bit more interesting. Anyhow, I’m still amazed that Verayo is able to claim a failure rate of less than one in a billion, while still being able to distinguish two almost identical chips - my hat is off if that turns out to be the case. And just in case this single patent application was not enough for you, Verayo also has another patent that is focused on the cryptography aspect of the PUFs - knock yourself out.