There are so many interesting conferences, symposia, and panel discussions that it is pity that one cannot attend them all. As such, it is always nice when someone who does attend an interesting event, takes the time to post of few highlight. Even better when a nice succinct trip report with some observations and commentary is provided. This time, the thanks go out to Mike Demler, and his The World is Analog blog for providing excellent coverage from the 10th Annual Wireless Communications Alliance (WCA) What’s Hot and What’s Not in Mobility 2009 investor panel discussion that occurred last week in Santa Clara, CA. Part 1 of the report can be found here, and part two can be found here. The panel consisted of Eric Zimits (Managing Director, Granite Ventures), Dev Khare (Vice President, Venrock), Tim Chang (Principal, Nortwest Venture Partners, and Scott Raney (Partner, Redpoint Ventures), and was moderated by Scott Ellison (VP Mobility Wireless, IDC). I encourage you to take some time and read both parts as they contain some interesting highlights and observations on a variety of subjects including: venture capital, mobile - software, services, infrastructure, TV, health, commerce, and advertising - just to mention a few.

If you are only interested in semiconductor startup related comments, here are the key takeaways: Startup capital for fabless digital design startups is almost non-existent. And while that Panelists placed the blame on China’s plethora of fabless design startups, I’m more in agreement with Mike’s observation that it is the cost of developing chips on the leading edge process that has erased the value proposition for potential investors. The Panelists were in agreement on the fact that RF and analog areas where a much better opportunity for semiconductor startups mostly due the smaller team sizes that are needed. The number of RF and mixed-signal startups that we have covered on this blog over the last few months very much supports this notion. As a matter of fact, I would say that any startup that can take what is usually considered an analog design problem and can find a digital implementation for it stands a good chance of finding some funding especially in the wireless space. On a related note, Femtocells are also becoming increasingly of interest mostly due to the bandwidth overloading that is currently experienced by the majority of the wireless carriers. We covered a startup called Percello last year that specializes in basebend processors for the Femtocell market. Finally, on the mobile processor side of things, the panelists held a strong believe that ARM will eat Intel’s lunch over the next few years and displace Intel’s Atom processor in the netbook/smartbook and smartphone markets. Once again I have to agree with Mike that one should never underestimate Intel, even if they are a relative newcomer to the SoC space (disclosure: I do have an affiliation with Intel; however, the opinions on this blog are purely and completely mine, and are not reflective of Intel’s opinions and business strategy).

Every time semiconductor companies move to the next process node one thing is for sure, the variability of small devices will likely increase once again, much to the dismay of circuit designers. These same circuit designers will then go off and perform a myriad of simulations to figure out how to size all the gates in the design in order to mitigate the increased variability, and thus reduces its yield impact. Well, not matter how hard the process and design engineers try; there will always be some variability from chip to chip, die to die, waver to waver, and so on. As it turns out, there might be a hidden benefit in this variability that when utilized properly can be used as an identification feature to ensure that the purchased product is a genuine one. Enter Verayo, a semiconductor startup out of San Jose, CA currently developing Physical Unclonable Functions (PUF) technology. For a detailed overview of Verayo I encourage you to read this VentureBeat article by Dean Takahashi, and for a little technical dicussion continue right along here. Below is graphic that depicts a quick overview of the general idea:

Essentially, the PUF technology is a circuit that is implemented onto the chip itself. This circuit, when exposed to an input vector produces a unique output vector, which can then be utilized to uniquely identify the chip. When the chip needs to be identified, an input vector is supplied and compared against a database of correct answers for that serial number. Since each chip varies ever so slightly from the next one, this circuit essentially utilizes this variation to create a unique electronic fingerprint for each device. In a similar manner, Verayo has developed what it calls a CryptoPUF, which exploits chip variation to generate unique secret keys for each IC, thus preventing the ICs from having to store these keys somewhere in memory which makes them vulnerable to hacking.

I have to admit I would be profoundly interested in seeing the actual circuit that Verayo has developed to generate these output vectors given an input sequence. It seems to me that this circuit has two very contradictory requirements. On the one hand, it must be sensitive enough, so that when two chips vary only slightly it can still generate unique output sequences for both of them. On the other hand, it must be robust enough to reliably generate the same output given a specific input. And it must be able to do this over a wide range of atmospheric conditions. This patent application, filed by Verayo in September of last year, is probably as much information as we can expect to obtain for now. Essentially, it describes a similar circuit as shown above, consisting of two parallel delays paths mostly made up of muxes that are controlled by the input vector. The output of these two paths is then combined using an XOR gate, to create a single output bit result. Well, things are not quite that simple, the patent also throws in some possible sequencers and hash elements to make things just a bit more interesting. Anyhow, I’m still amazed that Verayo is able to claim a failure rate of less than one in a billion, while still being able to distinguish two almost identical chips - my hat is off if that turns out to be the case. And just in case this single patent application was not enough for you, Verayo also has another patent that is focused on the cryptography aspect of the PUFs - knock yourself out.

Earlier this year, Mark Horowitz gave a talk at the 1st Berkeley Symposium on Energy Efficient Systems titled “Why Design Must Change: Rethinking Digital Design.” I did not have the chance to attend that symposium, but was lucky enough to attend an encore presentation by Mark a few days ago at the University of Texas, Austin as part of the Computer Architecture Seminar Series. If you don’t know who Mark Horowitz is then you truly must have been hiding underneath a rock. Suffice it to say he is pretty well regarded in the electrical engineering community, having received several best paper awards over the years, being the current chair of electrical engineering at Stanford University, and also having co-founded a little company called Rambus – so yes, when he speaks people generally tend to listen. The complete presentation slide as well as a recording of the Berkeley presentation can be found here . What follows below is quick summary of the talk and s few comments of my own.

The main point around which the talk revolves is as follow: Design costs and power dissipation have over the last decades gone through the roof. The good news is that some of the major contributing factors such as die growth and super frequency scaling have somewhat stopped. The bad news is that voltage scaling has also hit some limits. As voltage seizes to scale downwards, our biggest tool for scaling energy becomes significantly less effective. Mark is not optimistic on overcoming these challenges since overcoming limitations set by fundamental physics is rather difficult. For example he is very concerned about the on/off current ratio, which is a valid concern, but with regards to that I’m fairly certain that for several of the upcoming process generations, the process engineers have quite a few neat tricks up their sleeves. Mark is convinced that while silicon is not going away any time soon, the growth rate is going slow down significantly and eventually we will think of silicon the same way think about concrete and steel. Thus, instead of hoping that the process guys will save the day, we really need to figure out how to use what we already have, and by this he means we need to figure out how to reduce the amount of waste in our systems.

Some of the waste stems from the fact that maybe we are simply doing more work than we really need to – after all, if we do less work we will need less energy. This of course, could be caused by the fact that we are using the wrong tool for the job, and thus are creating more work than needed. The fact is that for specific tasks ASIC designs are more efficient that DSPs/Vector Engines, which in turn are more efficient than CPUs. Unfortunately, ASICs while efficient are also prohibitively expensive and few markets can justify their use. Which brings us full-circle back to where we started a few paragraphs ago: designing specific chips that do what we need, and do it well while consuming little power is way too expensive. The solution: A chip generator. Now, before you panic and say we’ve been there and tried that, relax, Mark is not talking about silicon compilers, that will take your nicely written high-level C++ algorithm and convert it into a perfectly working, super power efficient silicon that has been verified automatically - a nice dream indeed.

Instead, the message that Mark is sending to the chip and SoC design houses is that the designs they are putting together are most likely not the optimal solutions for what applications the customers have in mind. Instead, he would prefer if these companies instead of trying to guess what the customers want should rather put their efforts into developing a chip generator that would allow the eventual consumer to configure the final SoC as needed. Want half the cache: no problem - want to eliminate some not needed IOs: no sweat - need to configure your memory differently to optimize the performance, or add some extra math processing: no sweat. Essentially, let the customer figure out what they need, and you just focus on developing a tool that will put it together for them. I have to admit Mark, this does sound fantastic indeed. As a matter of fact, it is something that occurred to me a while ago while working on several SoCs that were very similar, but not similar enough for some of our customers, and thus required separate design spins. The problem is that while the chip generator might be more feasible than a silicon compiler, it is still something immensely difficult to pull off.

For one thing, if chips are difficult to design, it is quite conceivable that to design something that will design these chips might be even more so – is it worth it? Also, while process scaling might slow down one day, and library updates might become less frequent, that day is not here yet. Once again, if migrating a chip from one process to another is a major undertaking, optimizing the generator for the next process might be more work then re-doing some designs while adding a few customer requested enhancements. I’ve worked on several tools that had to be ported to new processes and most of the time it took more work than was anticipated. Finally, parameterizing a few things here and there is probably possible, but making things you as a company own configurable and then ensuring that they will play nice with third party IP provided by other companies, that can also be parametrized, is another story. Don’t get me wrong, I completely agree with Mark’s vision, and I do think that the future does require what he is suggesting, but process scaling really needs to slow down significantly for this to happen, and that is simply not yet the case. Too bad I forgot to ask him about the time horizon that he had in mind for the chip generator to become a reality.