We’ve all gotten accustomed to having digital cameras in our cell phones, and we’ve also gotton accustomed to the fact that if we want to take descent pictures we’ll need a second camera to do so. Slightly inconvenient, especially when travelling, but there is no easy way around it at this point. Well, according to Jess Lee, the president and CEO of InVisage Technologies, a startup out of Menlo Park, California, a couple years from now even the tiny image sensors in our cell phones will be able to produce fantastic images. The magic ingredient to make this happen is what the company calls QuantumFilm. The current crop of CMOS based image sensors have two major problems that only get worse with process scaling: First, they suffer from a poor fill factor since transistors and wires obstruct the incoming light, resulting in only about 50% of the incoming light reaching the silicon pixel. Second, their quantum efficiency, or in other words the conversion efficiency of the light that reaches the pixel, is only about 50%. As such, only about a quarter of the available light is captured by the image sensor, more often than not leading to less than stellar images.

Conversely, the QuantumFilm is composed of quantum dots, which in this care are semiconductors with light-capture properties, and is deposited on top of traditional CMOS wavers, and as such has a 100% fill factor. The silicon beneath the QuantumFilm is then utilized to convert the captured imprint of a light image into digital signals. InVisage claims that the QuantumFilm technology is capable of capturing of up to 90-95 percent of the light that reaches is. When combined, these two factors ought to yield performance about 4x higher than current image sensors, resulting in significantly higher quality pictures. Initial samples are expected to ship in Q4 of this year, and volume production is expected sometime in the middle of next year. The initial target market will include high-end mobile handsets and smartphones, which are expected to integrate this technology sometime in the 2012 timeframe. Currently, InVisage employs 30 people and has received more than $30 million in funding from RockPort Capital, Charles River Ventures, InterWest Partners and OnPoint Technologies. Below is a short video highlighting the technology from the DEMO Spring 2010 event – enjoy.

The term spacetime usually makes one think about physics, relativity, mathematical models, or at the very list some very interesting science fiction stories - Isaac Asimov anyone? But in this case, we are talking about Tabula, a fabless semiconductor startup out of Santa Clara, California developing programmable logic devices. Founded in 2003, the company currently employs 100+ people and has over the last few years filed over 150 patents, of which over 80 have been granted. The company is backed by several top-tier venture capital firms and has raised a total of $74 million in Series C funding alone. The company first appeared on our radar in October of last year when it made the updated EETimes Silicon 60 list; however, few details were available on the actual technology that the company was pursuing. Things changed at the beginning of this month though as the company emerged from stealth mode and announced what it calls breakthrough spacetime programmable logic architecture.

The basic idea behind the spacetime architecture is shown in the figure above. Essentially, the company is exploring time as a third dimension to reconfigure the logic in a given space, hence the name spacetime. In a regular FPGA, or for the matter in most chips, each area performs a specific logic function. Once that particular area is done performing the desired logical operation, the results are routed to the next stage, where additional logic is performed. Consequently, as the number of logic functions increases the chip area has to also increase in order to accommodate the additional logic. One solution to this problem would be to introduce a third vertical dimension by stack logic stages vertically; however, this would require complex manufacturing steps that are still under development. But, as mentioned beforehand, there exists another solution:  execute the first logic function, save the results, reconfigure the same space for the next function, and utilize the previous results as inputs to the new function. Repeat the process as needed to obtain the final output. Tabula refers to each of these function spaces as folds which are shown in the figure above as Folds 0 through 7. The number of folds, and hence reconfigurations available depends on the chip frequency, and can range from 2 at 800 MHz to 8 at 200 MHz. This approach offers a couple of advantages over regular designs: First, the design space it reused for different functions essentially providing a higher logic density and reducing the chip area needed. Second, since the data is stored locally to be reused in the next fold, no clock cycles are wasted routing data around the chip. One cool feature is that different sections of the chip can have different amounts of folds, which allows for fine granularity when optimizing functions. Another cool feature is that a memory cell with just a single read port can now mimic several read ports, where the number of ports is equivalent to the number of folds.

Now how is all this magic performed you might ask, of taking logic function and assigning it to a design space and separating it further into separate folds? This is obviously not a trivial task, and as such Tabula rightly decided to provide a compiler to automatically manage all of the hardware configurations, given a Verilog/VHDL input. Not much information on the compiler itself is currently published, and as such several questions remain unanswered. For example, it would be interesting to see how the compiler handles cases where there are a lot of conditional branches. Can different types of folds be loaded, i.e. different hardware configurations, based on the outcome of the previous fold. Or are the chip sections configured in such as way that only non-conditional logic is partitioned into folds?  How about, how is the synchronization handled between the different section when they run at different frequencies and have different numbers of folds? Finally, any information pertaining to power consumption is currently not being published, but is definitely of interest considering the number of configurations that happen on the chip any given cycle.  Nevertheless, the technology is exciting and it will be interesting to see what products the company announces in the near future.

There is nothing more interesting than competing technologies pursuing the same end product or application. In the blue corner, founded in 1985 and weighting in at close to 70 patents, please welcome the heavy-weight Anadigics from the GaAs camp. In the opposite red corner, please welcome the feather-weight challengers Black Sand Technologies and VT Silicon from the CMOS camp. All right, the above might be somewhat playful and exaggerated, but this does not mean that a real fight pitting Gallium Arsenide (GaAs) Power Amplifiers (PAs) vs. CMOS based PAs is not shaping up. Take for example the recent column over at EETimes titled "CMOS is the wrong technology for 3G handset PAs ," in which Mario Rivas, the president and CEO of Anadigics Inc., comes out swinging. His claims, paraphrased here for conciseness sake, are as follows: Today’s CMOS amplifiers are not capable of delivering sufficient linear output power to consistently overcome obstacles such as walls, ceilings and trees. Further, GaAs PAs can achieve close to 45 percent efficiency, implying that they are more efficient than CMOS based PAs. GaAs based PAs are more rugged and can deal better with changing environments conditions. And finally, GaAs technology has matured and issues are well understood, resulting in shorter design cycle times as opposed to new and emerging CMOS based implementations. Mario does concede that at some point CMOS based amplifiers might play a role, but not in the near term and not for 3G/4G applications.

Now contrast his claims to those made by the CMOS camp. For example, Black Sand Technologies proudly claims in their most recent press release, which discusses their acquisition of CMOS PA intellectual property from Silicon Laboratories, that replacing GaAs PAs with CMOS based ones improves manufacturing yield, performance, cost, battery life, and call quality. Pretty much countering all the claims made in favor of GaAs by Mario above. Add to this claims from VT Silicon, a startup pursuing silicon based PAs based on Silicon-Germanium (SiGe), of highly linear performance and once again lower production cost.  Add into the mix integrated control circuitry that allows for real-time performance adjustment and power management for the PAs, and ladies and gentlemen we have a fight on our hands! I will be the first one to admit that power amplifiers are absolutely not my forte but this does not preclude me from asking the following: Is Anadigics trying to protect their turf by touting the superiority of the GaAs solutions? Or, being a long time player in the PA space, are they simply utilizing their vast experience and knowledge and pointing out some of the limitations of the current CMOS based solutions. Conversely, are these startups overly optimistic in order to build hype and a market for their products? Will they be remembered as large on promises and short on delivery?  Time will tell, but regardless it will be an interesting conflict to watch as it evolves.