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Back in December I wrote a short post about magnetoresistive random access memory (MRAM), and a few competing technologies, as well as a short mention about Freescale’s current efforts. Given MRAM’s potential it should be of no surprise that Freescale is not the only name in town when it comes to MRAM. Micromem Technologies Inc., a Canadian fabless semiconductor device company based out of Toronto, announced the other week that they have manufactured a foundry grade fully functional MRAM cell, and intend to deliver it packaged for testing later this month. The company is currently proceeding with a test plan for a 64bit MRAM that builds on top of the current MRAM cell. The 64bit MRAM arrays are expected to be available for testing in three to four months. The currently produced MRAM cell is implemented in a Gallium Arsenide process, but the company intends to migrate its technology into to Silicon Germanium process as well to satisfy the lower cost, higher density memory market. Performance numbers for Micromem’s MRAM are currently no available, but the company expects to communicate the performance data in early February. Capacity wise Micromem is currently far behind players like Freescale who offer chips with up to 4Mbit capacity, but the company claims that its products are significantly less complex, and will be cheaper and less problem prone than competing products. The reduced complexity stems from the fact that Micromem is not utilizing the magnetic tunnel junction (MTJ) approach selected by many of its competitors, which introduces tunnel barrier and structural complexity, but instead opts for using a Hall Cross-Sensor (HCS) approach, thus the name HCS MRAM. Below is a diagram depicting the HCS device concept taken from the Micromem’s press release describing their successful HCS test. Micromem is initially targeting radiation hard applications, radar systems, satellites and sensors with their technology. Overall the technology seems promising; however, it is hard to make a call without any performance numbers so that it can be compared to other MRAM implementation. And while the company has successfully implemented a single bit, it will be interesting to see how their technology scales to larger arrays, and whether the HCS approach will really yield cheaper and more reliable MRAMs than the MTJ approach.

The National Venture Capital Association (NVCA) recently posted their annual VC investment prediction survey results for 2008. Conducted in December of this year, the survey included predictions from more than 170 respondents. Overall, the total amount of investment expected for ’08 is in the 20-29 billion dollar range, which is at best a slight increase over ’07 and a far cry from the 100 billion dollar level that was reached in 2000. The top three investment regions that VCs are most leery of are South America, China and Eastern Europe. Although VCs seem to be concerned about these regions, it is unlikely that these concerns will be a show-stopper for deals that will take place in these regions, as long as the potential rewards are large enough. As expected, clean technology startups are poised to experience the highest growth in investment, followed by media, biotech and internet startups. Flat to moderate investment growth is expected for medical device, wireless telecom, and software startups. However, a staggering 50% of the respondents expect a decrease in semiconductor investment, with another 37% expecting the investment to stay about flat. On the flipside, VCs also predict that clean technology will be the most overvalued industry in 2008, while semiconductors will be the most undervalued. Even though at first glance the above seems like rather gloomy news for semiconductor startups it is hard to overlook that most of the highest investment growth industries will require significant contributions and breakthroughs from semiconductor suppliers, especially on the low-power side. Thus, it seems not too far of a stretch to surmise that as companies in the currently VC favored industries tackle difficult problems; semiconductor startups will rise to the challenge and assist them in their endeavors. These companies in turn will require venture funding themselves which might lead to an underestimated upswing in semiconductor funding as we progress through ’08. On the more general economic front, the VCs also address several other issues such as the sub-prime credit woes, oil prices, dollar strength, and take a shot at the upcoming presidential election in the United State.

Massive parallel processor architectures seem to be the new way to riches, or at least something that might earn you a few minutes in the spotlight. But what good is all the parallel processing power if hardly anyone is able to utilize it effectively? This is precisely the question that must have been asked by Ambric’s founders when they decided to start the company. Founded in 2003 and with a head count just short of sixty, Ambric made a splash with their Am2045 processor when it was introduced last fall. Fabricated in the 0.13 micron process, it featured 360 32-bit RISC cores that when all running at 333MHz could deliver a theoretical performance of about one trillion operations per second. What was even more interesting though was the novel programming approach that assumed that due to the abundance of cores, software objects could be mapped on a core by core basis, thus not having to share resources. This idea is depicted in the figure below, where the numbers 1 through 7 represent the individual cores that are linked via communication channels. When Ambric's compiler detects that a software object is a primitive object it maps it to a single processor, however, when more complex computations are required several cores can be combined into a composite object which than will host the more complex application.

Given the object oriented programming model; it is not surprising that Ambric chose Java as the fundamental development language for the processor. Utilizing the Eclipse development framework and a few proprietary language extensions, the task of programming this massive array of processors seems to require less of a learning curve than most other massively parallel architectures, that either force programmers to learn new and unfamiliar languages, or might even require the usage of Verilog or VHDL. This is likely to be a major advantage for Ambric, for time to market is important and the shorter it takes for programmer to start cranking out useful code rather than "hello world" applications, the more likely they are going to favor one architecture over another. Now, with all this Java talk, do not think of the Am2045 as a Java chip, for the source code is not compiled into Java bytecode, but rather directly into the native machine language. For a complete overview of the architecture as well as short programming and development tool discussion, take a look at the Microprocessor Report article by Tom R. Halfhill that Ambric was nice enough to post on their web-site. It has some very good illustrations and additionally discusses Ambric’s closest competitors.

In the meantime, Ambric has not been standing still. At the beginning of November, it was reported that Ambric was nearing the close of a $30 million funding round that would bring the total funding for the company to $51 million to date. Additionally, the company has also been busy working on delivering the Am2045B processor to market. Compared to the AM2045, the Am2045B delivers a 40 percent increase in channel connectivity between the cores, and each core is now able to run at up to 350 MHz. Additionally, Ambric also claims that the power consumption has been reduced by 40 percent, or to about 6 to 12 Watts depending on the application. For about $325 a pop, in quantities of thousands, this is quite some processing power one can obtain with what looks to be a very promising development environment.

Sometimes the article quality over at EETimes.com makes you wonder whether the writing has been outsourced to a pupil at the elementary school level. Thus, it is nice and refreshing to read an article that is properly researched and well written. Case in point, Don Scansen’s article describing Intel’s 45-nm high-k metal-gate process and the accompanying analysis. As discussed by Don, the breakthrough that Intel has achieved at the 45-nm node is the incorporation of a high-k metal-gate into the process. The high-k material enables Intel to use a thick gate dielectric, which significantly reduces the gate leakage, while maintaining good conductivity through the transistor. Don also reveals that at the 65nm process node, the Intel gate dielectric was 13 percent thinner than the gate dielectric utilized by AMD. This would explain why Intel needed to incorporate a high-k material at the subsequent node, for thinning the dielectric any more was probably not a reasonable option. With the 45nm process Intel is expecting a leakage improvement in the neighborhood of 10x. The article also gives us an idea about the performance that Intel can expect: At 1.3v, I_on for the nfet and pfet are estimated to be 1.66 mA/um and 0.71 mA/um, respectively. The leakages for the nfet and pfet are expected to be 37 nA/um and 45 nA/um, respectively. An interesting observation that Dan makes is that Matsushita/Panasonic actually beat Intel to the 45-nm node using immersion lithography vs. Intel’s dry approach. And while the gate technology utilized by Matsushita is traditional, the immersion technology enables the company to achieve tighter metal pitches than Intel. The article also delves into a brief discussion of the materials utilized as well as about future process scaling, but just in case all this information is not enough to satisfy your technical cravings, you might also be interested in reading an interview with several of the Intel researchers that partook in the development of the process over here.