The American economy has definitely seen better days, no secrete there, but how to get out of this mess is another issue. Economic problems manifest themselves in many ways, with the most spectacular being the failures of giant corporations that are supposed to represent the bedrock of the economy. Well, if the giants are failing, why not encourage startups and entrepreneurship to get the economy going again? This is along the lines that Sramana Mitra seems to be thinking in her latest article at Forbes.com.

A quite successful entrepreneur in her own right, having founded and sold several software/web startups, and a strategy consultant in Silicon Valley since 1994, Sramana suggest that what the government really ought to do is give the entrepreneur a stimulus package. The package she is suggesting is an entrepreneurship-friendly tax policy targeted at entrepreneurs, angle investors, venture capital firms, and large corporation. In her article she examines the particular policies for each of the aforementioned groups in detail, but overall they can be summarized as follows: A tax-free pool of income for entrepreneurs and angel investors that can be reinvested into new ventures, an elimination of payroll taxes for small companies, a tired tax-structure for venture capital firms to once again encourages them to take some risks and invest in early stage startups in return for a lower tax on deals realized from those investments, and finally, tax breaks for large companies to invest into small business that in some form or other can in turn utilize the products and service offered by these large conglomerates. These are some interesting ideas indeed and definitely something to contemplate, especially when looking for more of a long-term plan for the country rather than a short-term stimulus package like the last one that was implemented by the goverment.

If you are interested in entrepreneurship in general you might also want to periodically take a glance at Sramana’s own blog in which she covers a vast spectrum of Silicon Valley from web startups, to entrepreneurship strategy and stock discussions, and even the occasional semiconductor blurb. As a matter of fact, her post in mid June which analyzed Cadence’s hostile takeover attempt of fellow EDA tool develop Mentor Graphics caused quite a discussion amongst her readers.

Venture capital money has been tight for semiconductor startups recently, but as always there are exceptions to the rule. One hot area is digital amplifiers. We wrote about digital amplifiers and BlackSand technologies in particular here and here. The other hot area is programmable transceivers, which is where BitWave Semiconductor comes into play. The company was formed in 2004 with the mission to assist cell phone manufacturers by reducing the number of chips needed to support all the different wireless standards, thus enabling them to offer more features in a smaller package and at a lower price. If you don’t think there are that many wireless standards, you might want to reconsider: GSM, WCDMA, HSDPA, HSUPA, AMPS, NAMPS, CDMA, CDMA2000, 1xRTT, EV-DO, CDPD, DVB-H, MediaFLO, DMB, Wi-Fi, WiMax, WiBro, UWB, Bluetooth, GPS, DAB, AM/FM, DECT, etc.

The solution to this mess, at least according to BitWave, is what the company calls Softranceiver Technology, which according to their website is the combination of “the art of analog with the science of digital.” Essentially, the Softranceiver architecture integrates digital control for many of the analog components. Thus, an API can be utilized to set proper registers which in turn control the output of the analog blocks. The result is that a single transceiver can be programmed to support many different wireless standards, significantly reducing the component integration costs. BitWave’s approach differs significantly from software-defined radio (SDR) in that it does not rely on digitizing the incoming signal via an analog-to-digital converter (ADC) and then processing it via a DSP, which according to BitWave’s President and CEO Dr. Michael Farese, leads to high-power consumption and has not been implemented successfully in a mobile device. An interview with Michael in which he describes several additional Softranceiver advantages can be found over at WTRS.

Currently, the Softranceiver is slated for volume production and general availability in the second quarter of 2008, and will be branded as the BW1102 Softranceiver RFIC. To make the commercialization happen, the company raised an additional $10 million in B-round funding from Apex Venture Partners, TVM Capital, and Ecentury Capital Partners last month. Clearly, the applications of this technology extend far beyond cell phones to just about any device that requires multi-mode, multi-band wireless capability. The potential market for this technology seems very appealing given the current growth rate for mobile devices. As long as the API is reasonable, and the transceiver works as promised, the potential rewards for the company could be enormous.

Based out of Netanya, Israel Plurality has been working on multi-core designs since 2004. In 2007, the company offered a proof of concept chip that incorporated 16 32-bit RISC cores, and offered it to customers as an evaluation and development kit. Then, the company was supposed to follow this up with a 64-core 90nm commercial chip in Q3 of 2007. But unless I’ve missed the announcement, this commercial product seems to have never materialized. Maybe the company encountered some problems with the initial design, or maybe the 64 cores were simply a few too many to make the product cost effective in 90nm? - We will probably never find out.

Regardless, in February of this year Plurality announced that research has been completed on their HyperCore Architecture Line (HAL) of multi-core processors and hinted at an investment round that would finance the commercialization of a 256-core chip, now slated to hit the market some time in 2009. This round of financing occurred in July, and netted the company a nice $8m in funding. Other than the increased number of cores, not too much seems to have changed architecturally, at least on the high-level. The design still incorporates a hardware based synchronizer/scheduler that optimizes the load for each core, although the company hints at having filed several more patent applications which improve its performance. Additionally, the design continues to connect all the cores to a single shared memory, rather than allowing individual cores to have local caches.  Finally, the company is sticking by its task map programming model which requires the programmer to divide a particular algorithm into specific tasks that define dependencies. Plurality makes it sound as if this programming process is a piece of cake for a regular programmer, however, I would question whether a regular programmer can partition an algorithm efficiently into parallel tasks. Further, with this approach, quite a bit of work will be required to re-compile older programs for optimum performance - but that is generally the case anyhow. Optimally, Plurality should develop a compiler that would automatically generate a task map for their HyperCore processor; however, this has been tried many times before and is still very much the holy grail of parallel programming.