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Over the last few months we have seen several innovative semiconductor startups raise some serious money, nevertheless it seem that as a whole, Venture Capitalists (VCs) seem to be a pessimistic bunch at the moment - at least the three guys Rick Merritt interviewed for his "Silicon Stratups get the Squeeze" article. Among the VCs interviewed were Andy Rappaport from August Capital, Mark Stevens from Sequoia Capital, and Lip-Bu Tan from Walden International. The main reason for the pessimism is well know to anyone in the chip industry, namely the prohibitively high cost of bringing a new fabless semiconductor startup to market.

I won't recap Rick's whole article for you can read it on your own, but there were a few interesting takeaways. According to Andy, if companies doing big SoC designs adopt open interfaces, there will be a chance for startups to at least play a part in supplying designs for specific functions to be integrated onto the SoCs. Further, he points out that system designers will have to do more in software in the future as chip choices will become limited. Mark very much agrees with this point of view, adding that with IPO exits largely non-existent these days and with established companies paying less and less for acquisitions, the return on investment (ROI) for funding semiconductor startups is simply no longer there. Lip-Bu is even more pessimistic, arguing that a substantial percentage of the approximately 2,200 companies funded over the last decade will have to fold and that the R&D mantle will pass once more to the big chip makers. He further points out that plenty of talented engineers, who will not be interested in joining these conglomerates, will choose instead to pursue careers in the clean technology and solar areas. Of the three guys interviewed, Lip-Bu seems the one most committed to semiconductors, but you better approach him only if the majority of your company is going to be located in China, India, or Taiwan. He firmly believes that the semiconductor center is moving west rapidly. If green technologies are not your thing and you want to stick with semiconductors, you better brush up on your mixed-signal and analog skills since both Andy and Lip-Bu prefer these areas at the moment.

I'm somewhat surprised that not one of the interviewed VCs discussed opportunities for low-power semiconductor startups in the life-sciences area. It seems to me that this field in particular could benefit from novel analog and mixed-signal designs and should be well suited for startups. I'm also somewhat skeptical about the large sum of money, on the order of $100 to $200 million, that the VCs claim are needed to get a fabless semiconductor startups funded. Additionally, a budget of $2 million dollars for a verification team per month as claimed by Andy seems unreasonable for a startup - even large chip design houses would find this to be expensive. Most companies we have written about on this site fall somewhere in the $20 - $60 million range when it comes to total funding, which while not cheap compared to a software startup is a far cry from the numbers that the VCs are suggesting. It almost seems that the exaggerated price tag that VCs are attaching to semiconductor startups is their indirect way of saying that they have found cheaper investments that have a quicker ROI elsewhere.

We first covered Powervation and the company’s Auto-Control DC/DC technology at the beginning of this year, while mentioning several other startups that were developing digital solutions for typically analog problems. A few months have passed and Powervation recently notified us that the company’s inaugural product, namely the PV3002 has become available. The PV3002 is an Auto-Control Dual Phase Digital Power IC and is targeted at the Computing, NetComms, and Storage markets, although many additional applications will surely take advantage of it. The PV3002 consists of a Digital Signal Processor (DSP), a RISC processor, and several analog blocks to make it a complete mixed-signal System-On-a-Chip (SOC). It can provide 1 or 2 phase operation and several of these ICs can be utilized in parallel to enable load sharing. As mentioned in our previous post, the key feature of this IC is its ability to monitor the output voltage in order to compensate for variations in line, load, capacitance, and inductance.

Performance and stability are provided through the use of a feedback loop for which the compensation level is controlled dynamically through a single parameter referred to as “MOJO.” The exact implementation of MOJO is obviously a trade secret, but one can obtain somewhat of an idea about what it entails from several publications. The company’s own website has a nice little primer titled DC-DC conversion with Auto-Control, which examines the typical digital DC-DC converter design, the inherent limitations brought on by the digital feedback loop, and how adaptive control can relax some of the performance constrains while still keeping the system stable. If you want to delve a little deeper and have IEEE access, you can find the following two recently published papers: Current Share in Multiphase SMPCs by Digital Filtering and Current Share in Multiphase DC-DC Converters Using Digital Filtering Techniques. Anthony Kelly, Powervation’s VP of Digital Control, must be one busy guy for all of these publications are authored by him.

The PV3002 comes in a 5x5 mm package and can deliver up to 80A to the load. The key parameters for the IC are specified in the table above. Tests at beta sites have show a 10% efficiency improvement at light load over existing solutions and a gain of up to 30% in system energy savings. Since the power-converter is completely self-contained, it can be plugged into any board and operate directly without any user intervention – this is referred to by Powervation as Plug-and-Power technology. Should some configuration be necessary, a Digital Power Center Interface GUI is also provided to make the configuration a breeze. In quantities of 1000, the PV3002 is currently available at $2.75 a pop.

While on the topic of novel memories, we might as well continue down this path, this time with a transistor-less memory cell designed for non-volatile memory products. Before delving into the memory cell details and the associated physics, a little info about the company, namely Unity Semiconductor, might be of interest. Based out of Sunnyvale, CA and founded in 2002, Unity Semiconductor emerged from stealth mode just about a month ago as it announced that it raised additional $22 million in Series C funding. This brings to total amount of funding that the company has received to a very respectable $75 million over the last few years, proving that an interesting idea in the semiconductor space will attract some serious money. The company was founded by Darrell Rinerson, Ed Ward and David Bostwick, all of whom seem to have had stints at some of the major semiconductor companies, including Micron and AMD. It is fairly unusual for a company to wait this long before existing stealth-mode, but just like with the device physics that took time to calculate, Unity Semi has also been calculative on how to penetrate the market and maintain control of their new conductive metal oxide and ionic motion (CMOx) technology. For this purpose, the company has amassed a war chest of patents before existing stealth-mode. How Many? How about in excess of 60 granted and another 90 applications currently pending, so feel free to knock yourself out examining them.

As mentioned before, the technology is targeted at the non-volatile memory (NVM) market which the company beliefs will grow to more than $25 billion by 2013. Currently, this market is being served by NAND flash technology; however there is a concern in the industry that NAND technology scaling might be reaching its limits. Hence, the recent spur in the development of new technologies that are to replace NAND flash including: resistive ram (RRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), magneto-resistive ram (MRAM), multi-chip packaging (MCP), and finally 3D-memory. Unity Semi briefly discusses the cons for each of these technologies in section 7 of this document. The company intends to tape-out a 64-gigabit product in the first half of 2010 and ramp up to volume production in the first half of 2011.

The figure above shows a cross section of the CMOx technology. On a high level, through the application of a high electric field across the tunnel oxide (TO) layer, the charge buildup in the tunnel oxide can be controlled which leads to a change in the trap-assisted tunnel current through the oxide, or in other words a change in the device resistance. If that just went over your head, you’re not the only one for sure; thankfully Unity Semiconductor has a presentation that discusses all of this in detail, including oxygen ion mobility and the associated memory effect. This is a very good presentation indeed and a detailed paper is included as well, so it is well worth your time. The company claims that the current difference between the two resistive states is approximately 10x and that the program and erase times are in the 1us range at +/-3V. Compared to flash NAND technology, Unity Semi is claiming a 4x density improvement and a 5 – 10x write speed improvement.

Overall, Unity’s technology is interesting and impressive at the same time, which explains why the company has been able to raise this much capital. The BEOL approach to commercialization, where the memory layer with CMOx technology is deposited on top of a regular CMOS logic layer by a secondary fab seems possible as well, although it will require a good partnership with an integrated device manufacturer (IDM). At the same time, NAND flash technology should not be written off too quickly. For years, people have predicted the end of transistor scaling due to various reasons, and yet the scaling continues and if you talk any of the major semiconductor players you will find them to be optimistic about being able to continue this trend for several process nodes to come. From published material it seems that the program vs. erase current is predicted to scale with device size, but it will be interesting to observe whether Unity Semi can maintain the 10x difference, especially as the technology is moved to next process nodes. On the flip-side, because of the BEOL approach, the company does not need to necessarily move to the latest and greatest process, since the CMOS logic layer is able to use a different process than the CMOx memory layer, which is a very nice option to have.

In February we briefly reviewed some of the emerging technologies listed by the MIT Technology Review, as pertaining to computing and electronics. One technology that we mentioned was Racetrack Memory, a technology that uses U-shaped magnetic nanowires in conjunction with a spin current to propagate magnetic patterns along the wire. It seems that since then MIT Technology Review has published a four minute video interview with Stuart Parkin, an IBM Research Fellow, discussing Racetrack Memory on a high level. It is a very nice little primer on this topic and might be of interest to anyone dealing with memory design and technology. The video embedded below is a much longer interview with Stuart as conducted by Fast Company TV. In this video, Stuart discusses Magnetic Memory, Racetrack Memory, and several other related things. A couple warnings about this video: The interviewer does not seem to really have a good handle on this topic, so bear through his less than stellar questions or attempts at humor, and wait for Stuart’s answers for they are a lot more interesting than the actual questions. Also, the audio volume in the interview is rather low, with the exception of the interviewer occasionally laughing hysterically directly into the microphone: a less than enjoyable experience. Nevertheless, the interview has some interesting content that might be of interest to some.