ChipCrunch.com

As discussed in a recent post, for the last few years power consumption has become one of the predominant issues in chip design, leading the industry down the path to multi-core processors and beyond. But clever architectural designs and sophisticated circuit techniques are only a few of a myriad of ways in dealing with the problem – how about improving the way chips are being cooled? This might seem at first like a band aid for power inefficient design, until the realization sets in that the industry is way past the point where a band aid might help and that already there are major problem with cooling chips; simply take a look at some of the monstrosities that can be found in desktop PCs and servers these days. Well, there might be some relief on the horizon, curtsey of Purdue University and their recent breakthrough in chip cooling. Using what the team refers to as ionic wind engines, the researchers were able to increase the heat-transfer coefficient by 250% percent when combined with a traditional fan.  A higher heat-transfer coefficient indicates a more efficient cooling process, thus leading to a possible decrease in heat-sink and fan sizes that might be required to cool a particular component, which in turn might enable thinner electronic devices.

The key idea that leads to the vastly improved heat-transfer coefficient lies in the research team’s ability to increase the airflow at the surface of the chip, which is where the ionic wind engines come into play. These engines are created through closely spaced electrodes near the chip surface. When voltage is applied, electrically charge atoms, or ions, travel between the negatively charged electrode and the positively charged electrode. However, on their journey they encounter positively charged air particles, and become positively charged atoms themselves. Instead of continuing their journey the positively charged atoms do a u-turn so to say and proceed back to the negative electrode, thus completing the ionic wind engine. The oppositely charged electrodes are not placed next to each other as one might initially assume, but rather are placed vertically on top of each other with a fixed spacing in-between. This minimizes the no-slip effect that is caused when air flows over an object, by ensuring that the molecules closest to the surface of the object don’t remain stationary.  In other words, the ionic wind engines ensure there is a good molecule circulation away from the chip surface, where it is needed most – which is not the case with traditional air-based cooling.

There is still plenty of work that needs to be done and commercial applications are not expected for at least another three years by which time the team hopes to have the technology working reliably at the micron scale. Nevertheless, some cooling relief seems to be on the horizon.

Not so long ago, the name of the game and the claim to fame was processor speed and megahertz. But as with most technology related things, the landscape changes quickly. These days, it is all about who can do more with less; less power that is. To approach this challenge, companies have to some degree been simplifying their cores, and instead of raising the megahertz count have been increasing the core count. The argument being, that several cores running slower but in parallel are more efficient than one core running at maximum speed, from the throughput and power envelope level point of view. However, it does not take a genius to figure out that if you put enough cores onto a single die, the power envelope per core decreases if the overall power for the chip is to stay the same.  Additionally, as you increase the core count, the die area for the chip is likely to increase, which can lead directly to yield problems.  A less leaky process and smaller feature sizes are no substitute for sound power management techniques and smart design. Addressing this very issue, Heinrich Hillmayr from Texas Instruments’ (TI) German division, posted an interesting article titled Minimizing Power Consumption at the Chip Level over at PowerManagementDesignLine.com (This must be one of the longest domain names I’ve ever come across!). If you are a seasoned circuit designer you can skip the first page of the article which briefly describes the basic relationships between voltage, leakage and dynamic currents, and power. If not, this might be a nice little review especially if you have an interview coming up. The second page is where the article gets interesting. In a perfect world there would be neither variation in a waver nor any variation between wavers, but semiconductor manufacturing is far from perfect. Thus in some regions, transistors are stronger than the nominal transistor, meaning that at a given voltage they conduct more current, while in other regions they are weaker and thus conduct less current. This causes two problems: Transistors that are located in the strong region will have a higher leakage current thus increasing the overall core power, while circuits in the weak region will have a problem meeting speed targets. The idea therefore is to diagnose the strength of the silicon, and to lower the voltage in strong silicon regions in order to decrease leakage currents while still meeting timing. The article does not disclose whether the silicon strength is determined by some sort of on-die sensors but simply states that the mechanism is based on embedded information.  I imagine that designing an on-die sensor to accurately determine transistor strength could be quite challenging, but not impossible. Whether such a design would be cost effective in the end is of course another matter. The article also describes voltage scaling based on temperature and has several charts to explain the details mentioned above and is definitely worth a quick glance.

Through-silicon vias (TSV) technology could be present in chips by the end of this year or at least at the beginning of 2008. At least this is what Jan Vardaman, the president and founder of semiconductor packaging consulting firm TechSearch International, concludes in his article titled “3-D Through-Silicon Vias Become a Reality .” It is no secret that most designers could envision many ways in which these vertical interconnects could be utilized to decrease timing problems. For example, consider the ever increasing cache sizes that can be found on chips these days. If one could fold these structures in 3D rather than laying them out in 2D, the vertical interconnects could shorten the lengths of global interconnects. Additionally, floor plans could be optimized to arrange units that sit in critical paths to be stacked vertically to reduce routing distance and obtain better timing closure. But so far, while many research projects have been touting the benefits of vertical interconnects, very little of this technology has made it into commercial applications. According to Jan this is likely to change in the near future as TSV technology is moved from the research stage into the commercialization stage.

His article, which is posted over at Semiconductor International, is a short overview of TSV technology, and can be us as a springboard for additional research for the interested reader. Jan gives an extensive summary of companies and institutions that have on-going research on TSV technology. He also gives a nice overview of the three main approaches to TSV, namely a front-end process which uses deep-trench capacitor technology to create the vias, a process were vias are etched through set-aside exclusion zones, and finally a process where vias are created through the redistribution of pads and via streets. It is a relatively short read with some good illustrations so if you are interested in this topic give it a read.

There were several announcements and articles during Intel’s developer Forum in Beijing in April regarding FPGA-FSB; however, it seems the excitement seems to have settled since then. This frankly is a little puzzling, considering the fact that Intel is allowing for others to use their FSB to communicate with the rest of the systems, which seems rather exciting. Usually, the barrier to entry for developing high-performance components to work with the rest of the system was pretty high. One could either opt to develop an entire board that would plug into one of the existing slot on the motherboard, or one could go the external route and interface through one of the external connectors. But for really high-performance computing, neither of the beforehand mentioned solutions was really a good answer. With this new plug-in possibility, a company only needs to obtain one of the socket compatible FPGA chips and then they can develop from there. The FPGA already contains all the functionality to connect with the Intel FSB, so the developers can focus on the actual co-processing they want to provide, and on the software which will take advantage of it. While the barrier to entry is still not as low as that for internet applications and a dot-com style gold rush is not to be expected, potentially several new startups could emerge that could take advantage of the fact that any new hardware designs they might conceive off could be prototyped and interacting with the rest of the systems in a rather short time. The idea itself of having an FSB compatible FPGA chip is not exactly new, a company called DRC Computer has been providing such chips for multi-way AMD Opteron systems now for over a year; however, Intel’s adoption of the concept has significantly expanded the market for potential startups.