Technical Bits

Sometimes the article quality over at EETimes.com makes you wonder whether the writing has been outsourced to a pupil at the elementary school level. Thus, it is nice and refreshing to read an article that is properly researched and well written. Case in point, Don Scansen’s article describing Intel’s 45-nm high-k metal-gate process and the accompanying analysis. As discussed by Don, the breakthrough that Intel has achieved at the 45-nm node is the incorporation of a high-k metal-gate into the process. The high-k material enables Intel to use a thick gate dielectric, which significantly reduces the gate leakage, while maintaining good conductivity through the transistor. Don also reveals that at the 65nm process node, the Intel gate dielectric was 13 percent thinner than the gate dielectric utilized by AMD. This would explain why Intel needed to incorporate a high-k material at the subsequent node, for thinning the dielectric any more was probably not a reasonable option. With the 45nm process Intel is expecting a leakage improvement in the neighborhood of 10x. The article also gives us an idea about the performance that Intel can expect: At 1.3v, I_on for the nfet and pfet are estimated to be 1.66 mA/um and 0.71 mA/um, respectively. The leakages for the nfet and pfet are expected to be 37 nA/um and 45 nA/um, respectively. An interesting observation that Dan makes is that Matsushita/Panasonic actually beat Intel to the 45-nm node using immersion lithography vs. Intel’s dry approach. And while the gate technology utilized by Matsushita is traditional, the immersion technology enables the company to achieve tighter metal pitches than Intel. The article also delves into a brief discussion of the materials utilized as well as about future process scaling, but just in case all this information is not enough to satisfy your technical cravings, you might also be interested in reading an interview with several of the Intel researchers that partook in the development of the process over here.

There are many companies working on replacement technologies for current memories. From T-RAM Semiconductor’s Thin-Capacitivel-Coupled-Thyristor (TCCT) technology, to Innovative Silicon’s Z-RAM, and Freescale’s Magnetoresistive Random Access Memory (MRAM). So far these companies have delivered a lot of papers and presentations, patent filings, a few licensing agreements, and even several consumer samples. But can these technologies really replace DRAM, Flash, and SRAM? The other day designnews.com, posted a short article titled: MRAM Shows Potential to Move Beyond Flash, SRAM. The article is mostly a summary of the advantages that MRAM offers over DRAM and Flash, including MRAM’s ability to retain data even when completely turned off and its superior write performance and endurance when compared to Flash. Freescale has a very nice technical brochure that explains the MRAM technology in detail, in case you need some bedtime reading. Currently, Freescale offers three different MRAM parts all of which run at 3.3V. Personally, I think that MRAM technology has real potential to take off once Freescale figures out how to lower the voltage and embed some of the MRAM technology into its SOC products. For example, a last level cache could benefit from this technology since shutting it off to conserve power would no longer require for all the data to be evicted from the cache first to not compromise the integrity of the system. Whether or not MRAM will be utilized this way will depend on the read and write speeds of MRAM as compared to SRAM at these lower voltages, as well as on area demands and noise tolerance. Nevertheless, it is nice to see that in the near future circuit designers might have a larger choice of technologies from which they will be able to choose when designing memories.

As discussed in a recent post, for the last few years power consumption has become one of the predominant issues in chip design, leading the industry down the path to multi-core processors and beyond. But clever architectural designs and sophisticated circuit techniques are only a few of a myriad of ways in dealing with the problem – how about improving the way chips are being cooled? This might seem at first like a band aid for power inefficient design, until the realization sets in that the industry is way past the point where a band aid might help and that already there are major problem with cooling chips; simply take a look at some of the monstrosities that can be found in desktop PCs and servers these days. Well, there might be some relief on the horizon, curtsey of Purdue University and their recent breakthrough in chip cooling. Using what the team refers to as ionic wind engines, the researchers were able to increase the heat-transfer coefficient by 250% percent when combined with a traditional fan.  A higher heat-transfer coefficient indicates a more efficient cooling process, thus leading to a possible decrease in heat-sink and fan sizes that might be required to cool a particular component, which in turn might enable thinner electronic devices.

The key idea that leads to the vastly improved heat-transfer coefficient lies in the research team’s ability to increase the airflow at the surface of the chip, which is where the ionic wind engines come into play. These engines are created through closely spaced electrodes near the chip surface. When voltage is applied, electrically charge atoms, or ions, travel between the negatively charged electrode and the positively charged electrode. However, on their journey they encounter positively charged air particles, and become positively charged atoms themselves. Instead of continuing their journey the positively charged atoms do a u-turn so to say and proceed back to the negative electrode, thus completing the ionic wind engine. The oppositely charged electrodes are not placed next to each other as one might initially assume, but rather are placed vertically on top of each other with a fixed spacing in-between. This minimizes the no-slip effect that is caused when air flows over an object, by ensuring that the molecules closest to the surface of the object don’t remain stationary.  In other words, the ionic wind engines ensure there is a good molecule circulation away from the chip surface, where it is needed most – which is not the case with traditional air-based cooling.

There is still plenty of work that needs to be done and commercial applications are not expected for at least another three years by which time the team hopes to have the technology working reliably at the micron scale. Nevertheless, some cooling relief seems to be on the horizon.