ChipCrunch.com

A little over a year ago we briefly discussed through-silicon vias (TSV). We examined some potential advantages and provided a link to a little TSV primer. Back then, the projection was that we ought to expect chips featuring TSV by the beginning of 2008. And while a few ICs here and there have been manufactured using TSV, a general standard was lacking thus slowing adoption across the industry. To overcome this problem, the 3D-IC Alliance, whose founding members include Tezzaron Semiconductor and Ziptronix, has released a first standard for 3D integration, dubbed the Intimate Memory Interface Standard (IMIS) – could they really not come up with a better name? While complaining, what is up with the 3D-IC website? It is truly an eyesore, and bags for a makeover.

Anyhow, as with most standards, the specification is quite extensive coming in at over thirty pages, but keep in mind that tables and diagrams take up a lot of that space.  The contents cover pin specifications and pin usage direction for most common memory types and their variations. Following the pins, the actual surface and target requirements are discussed at length. This section is split into three categories: Direct Bond Interconnect (DBI) which is championed by Ziptronix, Copper to Copper Bonding which is backed by Tezzaron under the FaStack brand, and a third category which at this point is undefined and reserved for future use. The final section is a short discussion of footprint diagrams and their variations.

As mentioned in our prior post, there are some immediate advantages that come to mind: shorter interconnect paths and more compact floor plans that no longer need to account for large caches, however, what we missed are the possible implications for Integrated Circuit (IC) security. On this topic, Tezzaron has a short paper which within the space of a couple pages, discusses on a high-level some of the reverse engineering techniques, as well as the two major security advantages for 3D ICs. To summarize, the first advantage is that if one of the layers in the stack is face-up while the connecting one is face-down, the outside surfaces would consist only of I/O pads, making etching and de-layering difficult. The second advantage is the fact that with a well defined interface, separate components can now be manufactured at different foundries, further reducing the risk that the final functionality of the part might be exposed. Obviously, the paper is intended as promotional material for 3D ICs, nevertheless it makes a few interesting points and is worth checking out for those interested in the subject.

Having covered magnetoresistive random access memory (MRAM) on several occasions it is time to move on to something a little bit more exotic, namely nanotubes. The January issue of the Nature Nanotechnology Magazine contains a very interesting article titled: Nanoscale Memory Cell based on a Nanoelectromechanical Switched Capacitor. Unfortunately, unless you are a subscriber to the magazine or might have access to it through your company, you will not be able to access the full article. Thankfully, nanowerk.com has a pretty nice write-up on the article and even obtained permission to reprint several of the illustrations. Looking at these illustrations, it can be seen that the proposed device is a three terminal device consisting of a source, drain, and gate. The source and drain both contain vertical multiwalled carbon nanotubes (MWCNT). The nanotube on the source, which is grounded, is covered with a dielectric layer which in turn is covered with a metal layer, thus completing the capacitor. The drain terminal is connected to what in a conventional design would be a bit-line and the gate terminal is connected to what would be a word-line. The mechanical switching occurs when bias voltages are applied to the drain and gate terminals. That is, when a gate voltage is applied but no drain voltage is applied, nothing happens. However, when both drain and gate voltages are applied, such that the gate voltage is higher than the drain voltage, the nanotube on the drain is subject to a repulsive electrostatic force from the gate and bends towards the source. If it bends far enough it establishes contact with the metal layer of the source and charges the capacitor effectively storing a logical one in the bit-cell, hence the name nanoelectromechanical switched capacitor (NEM).

The authors of this paper have only implemented the writing portion so far, but according to the paper, reading from the bit-cell would follow a similar sequence with the exception that the nanotube on the drain would be unable to make contact with a bit-cell that contained a logical one since even though it would still experience an electrostatic force from the gate, it would also be subject to a counter force from the charged capacitor, and thus no current would flow from the capacitor to any current sensing circuitry. All of the above is just a brief summary, the article contains all the dimensions used for constructing the device, a detailed description of the manufacturing method, all the voltages and capacitance numbers, and of course a few equations for calculating the switching speeds and effective capacitances, and is therefore definitely worth a look if you have access to it. While all of this is very preliminary work, it is nevertheless very fascinating and only gives us a small glimpse of all the esoteric structures that circuit designers might get to play with in the coming years.

Sometimes the article quality over at EETimes.com makes you wonder whether the writing has been outsourced to a pupil at the elementary school level. Thus, it is nice and refreshing to read an article that is properly researched and well written. Case in point, Don Scansen’s article describing Intel’s 45-nm high-k metal-gate process and the accompanying analysis. As discussed by Don, the breakthrough that Intel has achieved at the 45-nm node is the incorporation of a high-k metal-gate into the process. The high-k material enables Intel to use a thick gate dielectric, which significantly reduces the gate leakage, while maintaining good conductivity through the transistor. Don also reveals that at the 65nm process node, the Intel gate dielectric was 13 percent thinner than the gate dielectric utilized by AMD. This would explain why Intel needed to incorporate a high-k material at the subsequent node, for thinning the dielectric any more was probably not a reasonable option. With the 45nm process Intel is expecting a leakage improvement in the neighborhood of 10x. The article also gives us an idea about the performance that Intel can expect: At 1.3v, I_on for the nfet and pfet are estimated to be 1.66 mA/um and 0.71 mA/um, respectively. The leakages for the nfet and pfet are expected to be 37 nA/um and 45 nA/um, respectively. An interesting observation that Dan makes is that Matsushita/Panasonic actually beat Intel to the 45-nm node using immersion lithography vs. Intel’s dry approach. And while the gate technology utilized by Matsushita is traditional, the immersion technology enables the company to achieve tighter metal pitches than Intel. The article also delves into a brief discussion of the materials utilized as well as about future process scaling, but just in case all this information is not enough to satisfy your technical cravings, you might also be interested in reading an interview with several of the Intel researchers that partook in the development of the process over here.

There are many companies working on replacement technologies for current memories. From T-RAM Semiconductor’s Thin-Capacitivel-Coupled-Thyristor (TCCT) technology, to Innovative Silicon’s Z-RAM, and Freescale’s Magnetoresistive Random Access Memory (MRAM). So far these companies have delivered a lot of papers and presentations, patent filings, a few licensing agreements, and even several consumer samples. But can these technologies really replace DRAM, Flash, and SRAM? The other day designnews.com, posted a short article titled: MRAM Shows Potential to Move Beyond Flash, SRAM. The article is mostly a summary of the advantages that MRAM offers over DRAM and Flash, including MRAM’s ability to retain data even when completely turned off and its superior write performance and endurance when compared to Flash. Freescale has a very nice technical brochure that explains the MRAM technology in detail, in case you need some bedtime reading. Currently, Freescale offers three different MRAM parts all of which run at 3.3V. Personally, I think that MRAM technology has real potential to take off once Freescale figures out how to lower the voltage and embed some of the MRAM technology into its SOC products. For example, a last level cache could benefit from this technology since shutting it off to conserve power would no longer require for all the data to be evicted from the cache first to not compromise the integrity of the system. Whether or not MRAM will be utilized this way will depend on the read and write speeds of MRAM as compared to SRAM at these lower voltages, as well as on area demands and noise tolerance. Nevertheless, it is nice to see that in the near future circuit designers might have a larger choice of technologies from which they will be able to choose when designing memories.