Verayo, utilizing process variability as a feature

Every time semiconductor companies move to the next process node one thing is for sure, the variability of small devices will likely increase once again, much to the dismay of circuit designers. These same circuit designers will then go off and perform a myriad of simulations to figure out how to size all the gates in the design in order to mitigate the increased variability, and thus reduces its yield impact. Well, not matter how hard the process and design engineers try; there will always be some variability from chip to chip, die to die, waver to waver, and so on. As it turns out, there might be a hidden benefit in this variability that when utilized properly can be used as an identification feature to ensure that the purchased product is a genuine one. Enter Verayo, a semiconductor startup out of San Jose, CA currently developing Physical Unclonable Functions (PUF) technology. For a detailed overview of Verayo I encourage you to read this VentureBeat article by Dean Takahashi, and for a little technical dicussion continue right along here. Below is graphic that depicts a quick overview of the general idea:

Essentially, the PUF technology is a circuit that is implemented onto the chip itself. This circuit, when exposed to an input vector produces a unique output vector, which can then be utilized to uniquely identify the chip. When the chip needs to be identified, an input vector is supplied and compared against a database of correct answers for that serial number. Since each chip varies ever so slightly from the next one, this circuit essentially utilizes this variation to create a unique electronic fingerprint for each device. In a similar manner, Verayo has developed what it calls a CryptoPUF, which exploits chip variation to generate unique secret keys for each IC, thus preventing the ICs from having to store these keys somewhere in memory which makes them vulnerable to hacking.

I have to admit I would be profoundly interested in seeing the actual circuit that Verayo has developed to generate these output vectors given an input sequence. It seems to me that this circuit has two very contradictory requirements. On the one hand, it must be sensitive enough, so that when two chips vary only slightly it can still generate unique output sequences for both of them. On the other hand, it must be robust enough to reliably generate the same output given a specific input. And it must be able to do this over a wide range of atmospheric conditions. This patent application, filed by Verayo in September of last year, is probably as much information as we can expect to obtain for now. Essentially, it describes a similar circuit as shown above, consisting of two parallel delays paths mostly made up of muxes that are controlled by the input vector. The output of these two paths is then combined using an XOR gate, to create a single output bit result. Well, things are not quite that simple, the patent also throws in some possible sequencers and hash elements to make things just a bit more interesting. Anyhow, I’m still amazed that Verayo is able to claim a failure rate of less than one in a billion, while still being able to distinguish two almost identical chips - my hat is off if that turns out to be the case. And just in case this single patent application was not enough for you, Verayo also has another patent that is focused on the cryptography aspect of the PUFs - knock yourself out.