ChipCrunch.com

The term spacetime usually makes one think about physics, relativity, mathematical models, or at the very list some very interesting science fiction stories - Isaac Asimov anyone? But in this case, we are talking about Tabula, a fabless semiconductor startup out of Santa Clara, California developing programmable logic devices. Founded in 2003, the company currently employs 100+ people and has over the last few years filed over 150 patents, of which over 80 have been granted. The company is backed by several top-tier venture capital firms and has raised a total of $74 million in Series C funding alone. The company first appeared on our radar in October of last year when it made the updated EETimes Silicon 60 list; however, few details were available on the actual technology that the company was pursuing. Things changed at the beginning of this month though as the company emerged from stealth mode and announced what it calls breakthrough spacetime programmable logic architecture.

The basic idea behind the spacetime architecture is shown in the figure above. Essentially, the company is exploring time as a third dimension to reconfigure the logic in a given space, hence the name spacetime. In a regular FPGA, or for the matter in most chips, each area performs a specific logic function. Once that particular area is done performing the desired logical operation, the results are routed to the next stage, where additional logic is performed. Consequently, as the number of logic functions increases the chip area has to also increase in order to accommodate the additional logic. One solution to this problem would be to introduce a third vertical dimension by stack logic stages vertically; however, this would require complex manufacturing steps that are still under development. But, as mentioned beforehand, there exists another solution:  execute the first logic function, save the results, reconfigure the same space for the next function, and utilize the previous results as inputs to the new function. Repeat the process as needed to obtain the final output. Tabula refers to each of these function spaces as folds which are shown in the figure above as Folds 0 through 7. The number of folds, and hence reconfigurations available depends on the chip frequency, and can range from 2 at 800 MHz to 8 at 200 MHz. This approach offers a couple of advantages over regular designs: First, the design space it reused for different functions essentially providing a higher logic density and reducing the chip area needed. Second, since the data is stored locally to be reused in the next fold, no clock cycles are wasted routing data around the chip. One cool feature is that different sections of the chip can have different amounts of folds, which allows for fine granularity when optimizing functions. Another cool feature is that a memory cell with just a single read port can now mimic several read ports, where the number of ports is equivalent to the number of folds.

Now how is all this magic performed you might ask, of taking logic function and assigning it to a design space and separating it further into separate folds? This is obviously not a trivial task, and as such Tabula rightly decided to provide a compiler to automatically manage all of the hardware configurations, given a Verilog/VHDL input. Not much information on the compiler itself is currently published, and as such several questions remain unanswered. For example, it would be interesting to see how the compiler handles cases where there are a lot of conditional branches. Can different types of folds be loaded, i.e. different hardware configurations, based on the outcome of the previous fold. Or are the chip sections configured in such as way that only non-conditional logic is partitioned into folds?  How about, how is the synchronization handled between the different section when they run at different frequencies and have different numbers of folds? Finally, any information pertaining to power consumption is currently not being published, but is definitely of interest considering the number of configurations that happen on the chip any given cycle.  Nevertheless, the technology is exciting and it will be interesting to see what products the company announces in the near future.