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Plurality, more funding for HyperCore

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Written by Maciej Bajkowski   
Tuesday, 19 August 2008

plurality.comBased out of Netanya, Israel Plurality has been working on multi-core designs since 2004. In 2007, the company offered a proof of concept chip that incorporated 16 32-bit RISC cores, and offered it to customers as an evaluation and development kit. Then, the company was supposed to follow this up with a 64-core 90nm commercial chip in Q3 of 2007. But unless I’ve missed the announcement, this commercial product seems to have never materialized. Maybe the company encountered some problems with the initial design, or maybe the 64 cores were simply a few too many to make the product cost effective in 90nm? - We will probably never find out.

Regardless, in February of this year Plurality announced that research has been completed on their HyperCore Architecture Line (HAL) of multi-core processors and hinted at an investment round that would finance the commercialization of a 256-core chip, now slated to hit the market some time in 2009. This round of financing occurred in July, and netted the company a nice $8m in funding. Other than the increased number of cores, not too much seems to have changed architecturally, at least on the high-level. The design still incorporates a hardware based synchronizer/scheduler that optimizes the load for each core, although the company hints at having filed several more patent applications which improve its performance. Additionally, the design continues to connect all the cores to a single shared memory, rather than allowing individual cores to have local caches.  Finally, the company is sticking by its task map programming model which requires the programmer to divide a particular algorithm into specific tasks that define dependencies. Plurality makes it sound as if this programming process is a piece of cake for a regular programmer, however, I would question whether a regular programmer can partition an algorithm efficiently into parallel tasks. Further, with this approach, quite a bit of work will be required to re-compile older programs for optimum performance - but that is generally the case anyhow. Optimally, Plurality should develop a compiler that would automatically generate a task map for their HyperCore processor; however, this has been tried many times before and is still very much the holy grail of parallel programming.

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No.1 VP Sales and Marketing
I'd like to reply to Maciej's question about Plurality’s delay in introducing a 64-core 90nm commercial chip in Q3 of 2007, and whether Pluraltiy encountered some problems with the initial design, or whether it was too expensive to package 64 cores in 90nm. The answer to both questions is "no".

Developing such a chip is not a trivial matter. Just look at the slow progress from giants like Intel and AMD in developing manycore processors. Everyone knows that the design challenges are huge; otherwise there would have been a mass proliferation of manycore chips on the market by now. Instead there are few, and those few have many limitations.

Among the keys to optimal performance include efficient , user-friendly code compiling; fine-grain parallelism; scalability; efficient load balancing and management of the cores; low-latency, high-throughput core access; linear speedup; and high-speed memory access. Plurality has addressed all these issues and today (November 6, 2008) announced the release of an extensive set of development tools for evaluating HyperCore's performance.

Plurality's task-oriented programming model and related task-mapping greatly simplify the job of identifying task dependencies in order to partition an algorithm efficiently into parallel tasks. The days are long gone when a programmer could write serial code and rely on continuously increasing speed to improve performance. Instead, programmers today must understand the dependencies among the various threads in the algorithm. It is not realistic to think that one day there will be a compiler that can automatically and completely determine the threads’ dependencies. There must be some kind of human intervention. If the programmer does not understand the dependencies, the result will be poor code.

Understanding the dependencies among the threads is not so trivial. It is very difficult to trace the dependencies within code in current coding techniques because the dependencies are implicitly buried inside the code. The programmer must start to think in terms of identifying dependencies before writing the code, instead of trying to discover them afterwards. Plurality’s task map methodology enables the programmer to declare the dependencies as he writes or compiles the code.

The parallel programming process is not a piece of cake for even the best programmer. To the best of our knowledge, Plurality provides the average programmer with the most programmer-friendly software development mechanism for explicitly defining the dependencies among the threads.

Regarding the introduction of the 64-core chip, Plurality has decided to use 65nm process, which is superior to 90nm process for the price/performance/size/power consumption ratio that customers are seeking. We also will use 65nm process for our 256-core chip. The target date for delivery of the 64-core chip is Q2, 2009. The 256-core chip will be delivered in 2010.

Alan Singer,
Plurality VP Sales and Marketing
Submitted by alan, on 2008-11-06 02:59:27
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