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We first wrote about Semprius Inc. back in 2007 when the company raised $4.1 million in Series A funding. Back then the company was busy working on its micro-transfer printing technology which allows the company to transfer transistors from a traditional substrate onto other surfaces such as glass or plastic. Back then we wondered, given all the commercialization options,  which avenue Semprius would pursue and how successful it would be. Well, the last couple of years have shed some light on the company’s prospects. Semprius chose to initially focus on the production of low cost, high performance solar modules, in particular concentrator photovoltaic (CPV) modules for large-scale solar power generation. This move was first rewarded by a successful Series B round of funding in the middle of last year, which netted the company a nice $6.4 million. During the investment round the existing investors were joined by In-Q-Tel and the GVC Investment Fund. Then, an additional bonus followed later that year, when John A. Rogers who is one of the three original Semprius founders, received the MacArthur Foundation “Genius” Grant in the amount of $500,000. Finally, the company also appeared on the EETimes Silicon 60 List towards the end of the year.

2010 has barely started, and the company is once again collecting some funding. This time around, Semprius received a $1.5 million investment from X-FAB, a pure-play analog/mixed-signal semiconductor foundry based out of Erfurt, Germany, as part of a strategic development agreement. With this agreement, X-FAB will become the designated foundry for Semprius technology. This latest investment shows a couple things: First, the company is active on multiple fronts. While the solar applications are moving full steam ahead, the company is also actively marketing its technology for other applications. Second, X-FAB clearly believes that Semprius’ technology will be quite relevant in the field of printed electronics over the near term, and as such wanted to lock in potential customers which are likely to take advantage of it for its foundry business. Overall, Semprius has now received close to $12.5 million in funding and with the recent developments and positive press coverage things seem to be looking up for the company at the moment.

Marseille Networks, based out of Silicon Valley, CA is claiming a lot with their latest press release, but only partially reveals its hand. The company claims to have reinvented the fabless semiconductor development process through what it refers to as a virtual tape-out methodology. These claims become even more stunning, when one considers that, as pointed out by VentureBeat’s Dean Takahashi, the company has a mere 20 employees and has raised a paltry, by semiconductor startup standards, $5 million in funding. Claims like these could be easily dismissed as wishful thinking on part of the company’s founders, but Marseille’s introduction of a complete line of Quad-HD (2160p – 3840 x 2160) video processors for the flat-panel TV, PC, and A/V markets makes this a bit difficult. Especially, since the company maintains that these complex chips were developed in less than 12 months. As part of the company’s Video Through Virtualization (VTV) 1200 family of processor, these chips have native Quad-HD support and also perform up-scaling of legacy HD content to Quad-HD. From the company’s press release it is not clear if a demo utilizing these new processors was performed at CES this year. Maybe someone who stopped by Marseille’s booth at CES could comment on this?

And while specifications and block diagrams are available for the VTV-1200 family of processors on Marseille’s website and are generally self-explanatory, how exactly the virtual tape-out methodology works is significantly less clear. According to the company, the VTV platform which enables the virtual tape-out flow is a hybrid hardware emulation and software simulation environment which sits on-top of Marseille’s proprietary switch fabric. The VTV platform consists of four major components: Tools, Hardware, Libraries, and Methodology. The info on the company’s web-site seems to indicate that the hardware is FPGA based. The key benefit, as shown in the picture above, seems to stem from the customer’s ability to start developing their software before the final chip is delivered, which in turn the company suggest should save anywhere between 6 – 12 months in design time. Based on this I fail to see how this is really a reinvention of the fabless development process. There are plenty of companies in the chip industry that provide software based simulators and FPGA based emulators to customers way before they deliver the final silicon. Of course, there might be more to the virtual tape-out flow than might appear at first. Are customers allowed to modify the architecture, integrate custom IP, and then re-program the FPGA continuously to analyze the changes in performance? Are the changes then communicated back to Marseille’s to be integrated into the final IC? Maybe, but as stated before, it is not exactly clear from the information that Marseille’s has published so far.

The reports reiterating a VC winter for semiconductor startups just keep on coming, the latest one being from Gartner, discussed here. And yet, clever startups keep on beating the odds, by obtaining funding even given all this negative press. The latest of which is Arteris, an EDA startup specializing in providing SoC interconnect IP and tools, based on the company’s Network-on-Chip (NoC) architecture. Founded in 2003, with headquarters in San Jose, CA and an engineering design center in Paris, France, Arteris just completed a strategic investment round that netted the company $9.7 million in funding. The funding round was led by Qualcomm and ARM, who joined an impressive list of investors including Synopsys, DoCoMo Capital, Crescendo Ventures, TVM Capital and Ventech, in making it possible. Arteris’ technology supports ARM’s Advanced Microcontroller Bus Architecture (AMBA) out of the box, but according to the company can be easily extended to support proprietary bus protocols.

The idea for NoC, the company admits, was taken from applicable concepts in the computer network arena and then adapted to IC design. Arteris currently offers three separate tool chains, depending on the design complexity at hand: FlexWay, FlexNoC, and NoC Solution. FlexWay is targeted to enable designers to quickly replace their current Advanced High-Performance Bus (AHB) by offering improved performance, support for heterogeneous interfaces, and a verification engine to verify the interconnects and interface protocol coverage. FlexNoC, as the next step up, offers multi-protocol support, is optimized for high-throughput while minimizing area and power, and also offers a test suite that promises a 100% interconnect coverage along with functional coverage test on the component interfaces. The top of the line tool, NoC Solution, is target at very complex designs and offers additional features such a Quality of Service (QoS) support, and multiple clock and power domain support, just to name a few. It also features a DRAM scheduler that integrates with the NoC architecture as needed. In addition to the verification engine mentioned beforehand, NoC Solution also comes with a NoCcompiler and NoCexplorer which allow designers to quickly capture, configure, and evaluate their bus architectures.

With the number of components that are being integrated onto SoCs increasing constantly, the tools that Arteris offers might indeed become essential. Especially for smaller integration teams that do not have the resources to evaluate and design proprietary bus architectures for their SoCs. I definitely think that Arteris is on the right track by focusing on a specific problem, namely the bus network architecture, an area which is only going to get more complicated in the near future.

Every time semiconductor companies move to the next process node one thing is for sure, the variability of small devices will likely increase once again, much to the dismay of circuit designers. These same circuit designers will then go off and perform a myriad of simulations to figure out how to size all the gates in the design in order to mitigate the increased variability, and thus reduces its yield impact. Well, not matter how hard the process and design engineers try; there will always be some variability from chip to chip, die to die, waver to waver, and so on. As it turns out, there might be a hidden benefit in this variability that when utilized properly can be used as an identification feature to ensure that the purchased product is a genuine one. Enter Verayo, a semiconductor startup out of San Jose, CA currently developing Physical Unclonable Functions (PUF) technology. For a detailed overview of Verayo I encourage you to read this VentureBeat article by Dean Takahashi, and for a little technical dicussion continue right along here. Below is graphic that depicts a quick overview of the general idea:

Essentially, the PUF technology is a circuit that is implemented onto the chip itself. This circuit, when exposed to an input vector produces a unique output vector, which can then be utilized to uniquely identify the chip. When the chip needs to be identified, an input vector is supplied and compared against a database of correct answers for that serial number. Since each chip varies ever so slightly from the next one, this circuit essentially utilizes this variation to create a unique electronic fingerprint for each device. In a similar manner, Verayo has developed what it calls a CryptoPUF, which exploits chip variation to generate unique secret keys for each IC, thus preventing the ICs from having to store these keys somewhere in memory which makes them vulnerable to hacking.

I have to admit I would be profoundly interested in seeing the actual circuit that Verayo has developed to generate these output vectors given an input sequence. It seems to me that this circuit has two very contradictory requirements. On the one hand, it must be sensitive enough, so that when two chips vary only slightly it can still generate unique output sequences for both of them. On the other hand, it must be robust enough to reliably generate the same output given a specific input. And it must be able to do this over a wide range of atmospheric conditions. This patent application, filed by Verayo in September of last year, is probably as much information as we can expect to obtain for now. Essentially, it describes a similar circuit as shown above, consisting of two parallel delays paths mostly made up of muxes that are controlled by the input vector. The output of these two paths is then combined using an XOR gate, to create a single output bit result. Well, things are not quite that simple, the patent also throws in some possible sequencers and hash elements to make things just a bit more interesting. Anyhow, I’m still amazed that Verayo is able to claim a failure rate of less than one in a billion, while still being able to distinguish two almost identical chips - my hat is off if that turns out to be the case. And just in case this single patent application was not enough for you, Verayo also has another patent that is focused on the cryptography aspect of the PUFs - knock yourself out.