Startup Blurbs

The reports reiterating a VC winter for semiconductor startups just keep on coming, the latest one being from Gartner, discussed here. And yet, clever startups keep on beating the odds, by obtaining funding even given all this negative press. The latest of which is Arteris, an EDA startup specializing in providing SoC interconnect IP and tools, based on the company’s Network-on-Chip (NoC) architecture. Founded in 2003, with headquarters in San Jose, CA and an engineering design center in Paris, France, Arteris just completed a strategic investment round that netted the company $9.7 million in funding. The funding round was led by Qualcomm and ARM, who joined an impressive list of investors including Synopsys, DoCoMo Capital, Crescendo Ventures, TVM Capital and Ventech, in making it possible. Arteris’ technology supports ARM’s Advanced Microcontroller Bus Architecture (AMBA) out of the box, but according to the company can be easily extended to support proprietary bus protocols.

The idea for NoC, the company admits, was taken from applicable concepts in the computer network arena and then adapted to IC design. Arteris currently offers three separate tool chains, depending on the design complexity at hand: FlexWay, FlexNoC, and NoC Solution. FlexWay is targeted to enable designers to quickly replace their current Advanced High-Performance Bus (AHB) by offering improved performance, support for heterogeneous interfaces, and a verification engine to verify the interconnects and interface protocol coverage. FlexNoC, as the next step up, offers multi-protocol support, is optimized for high-throughput while minimizing area and power, and also offers a test suite that promises a 100% interconnect coverage along with functional coverage test on the component interfaces. The top of the line tool, NoC Solution, is target at very complex designs and offers additional features such a Quality of Service (QoS) support, and multiple clock and power domain support, just to name a few. It also features a DRAM scheduler that integrates with the NoC architecture as needed. In addition to the verification engine mentioned beforehand, NoC Solution also comes with a NoCcompiler and NoCexplorer which allow designers to quickly capture, configure, and evaluate their bus architectures.

With the number of components that are being integrated onto SoCs increasing constantly, the tools that Arteris offers might indeed become essential. Especially for smaller integration teams that do not have the resources to evaluate and design proprietary bus architectures for their SoCs. I definitely think that Arteris is on the right track by focusing on a specific problem, namely the bus network architecture, an area which is only going to get more complicated in the near future.

Every time semiconductor companies move to the next process node one thing is for sure, the variability of small devices will likely increase once again, much to the dismay of circuit designers. These same circuit designers will then go off and perform a myriad of simulations to figure out how to size all the gates in the design in order to mitigate the increased variability, and thus reduces its yield impact. Well, not matter how hard the process and design engineers try; there will always be some variability from chip to chip, die to die, waver to waver, and so on. As it turns out, there might be a hidden benefit in this variability that when utilized properly can be used as an identification feature to ensure that the purchased product is a genuine one. Enter Verayo, a semiconductor startup out of San Jose, CA currently developing Physical Unclonable Functions (PUF) technology. For a detailed overview of Verayo I encourage you to read this VentureBeat article by Dean Takahashi, and for a little technical dicussion continue right along here. Below is graphic that depicts a quick overview of the general idea:

Essentially, the PUF technology is a circuit that is implemented onto the chip itself. This circuit, when exposed to an input vector produces a unique output vector, which can then be utilized to uniquely identify the chip. When the chip needs to be identified, an input vector is supplied and compared against a database of correct answers for that serial number. Since each chip varies ever so slightly from the next one, this circuit essentially utilizes this variation to create a unique electronic fingerprint for each device. In a similar manner, Verayo has developed what it calls a CryptoPUF, which exploits chip variation to generate unique secret keys for each IC, thus preventing the ICs from having to store these keys somewhere in memory which makes them vulnerable to hacking.

I have to admit I would be profoundly interested in seeing the actual circuit that Verayo has developed to generate these output vectors given an input sequence. It seems to me that this circuit has two very contradictory requirements. On the one hand, it must be sensitive enough, so that when two chips vary only slightly it can still generate unique output sequences for both of them. On the other hand, it must be robust enough to reliably generate the same output given a specific input. And it must be able to do this over a wide range of atmospheric conditions. This patent application, filed by Verayo in September of last year, is probably as much information as we can expect to obtain for now. Essentially, it describes a similar circuit as shown above, consisting of two parallel delays paths mostly made up of muxes that are controlled by the input vector. The output of these two paths is then combined using an XOR gate, to create a single output bit result. Well, things are not quite that simple, the patent also throws in some possible sequencers and hash elements to make things just a bit more interesting. Anyhow, I’m still amazed that Verayo is able to claim a failure rate of less than one in a billion, while still being able to distinguish two almost identical chips - my hat is off if that turns out to be the case. And just in case this single patent application was not enough for you, Verayo also has another patent that is focused on the cryptography aspect of the PUFs - knock yourself out.

Competition in the RF Power Amplifier (PA) space is definitely heating up. Last month, Black Sand Technologies announced the world’s first 3G CMOS based RF PA. Earlier this month, VT Silicon, announced the world’s first silicon-based 4G PA. Based out of Atlanta, GA, VT Silicon is fabless semiconductor startup which was incorporated in 2002 and initially focused primarily on military applications. In 2007, the company kicked off efforts to commercialize some of the developed technology, specifically targeting WiMax applications. At about the same time VT Silicon raised $3.3 million in Series A funding from Menlo Ventures. VT Silicon’s first chip will be the VMF2500 WiMax/WiFi Front End RFIC, for which the block diagram is shown below.

Instead of gallium arsenide (GaAs), which is traditionally used for power amplifiers, VT Silicon intends to use Silicon Germanium (SiGe) BICMOS which has a significant cost advantage over GaAs, and as such should be of interest to mobile device manufacturers. The company has developed what it refers to as Linearity Enhancement Technology (LET), which improves the linear operating range of their amplifiers, resulting in less signal distortion and yielding a more power efficient system. It is this LET technology that enables the company to use SiGe instead of GaAs while still delivering competitive performance. Further, SiGe enables VT Silicon to integrate a complex CMOS control circuit directly onto the IC, which the company refers to as Intelligent RF. This circuitry can then be utilized to continually tweak the configuration of the PA to optimize performance for lowest power consumption based on factors such as battery voltage, temperature, or the TX power level. The CMOS circuitry also enables the IC to be software configurable. All in all, the VMF2500 becomes a single chip RF PA solution, as opposed to multi-chip solutions that are comment these days on the front end. The company expects the quiescent current for chip to be less than 45mA when in low-power TX mode. Samples for strategic partners are expected to become available in the 2nd quarter of 2010, with mass production targeted the follow in the 4th quarter.