ChipCrunch.com

The intervals at which EETimes.com updates their emerging startup list is very inconsistent, and so it comes that just three months after publishing their 6.0 list, which we analyzed here, they’ve published an updated 6.1 version. There really is not that much new on this updated list. Two companies have left the list, namely Tarari and Clear Shape Technologies. The former has been acquired by the LSI Corporation and the latter has been acquired by Cadence Design Systems. The respective press release for the acquisitions can be found here and here. Newcomers to the 6.1 list include Kenet Inc., Perpetuum Ltd., and Phiar Corporation. Kenet Inc is a fabless semiconductor company that specializes in mixed-signal solutions for portable electronics. It was founded to commercialize the FemtoCharge technology that was developed at MIT’s Lincoln Laboratory. Perpetuum is a startup that focuses on vibration energy-harvesting, enabling wireless and battery-free sensors. Finally, Phiar is developing nano-scale stacks of metal and insulators that enable devices that can operate at terahertz frequencies.

History is littered with examples where better technologies or vastly superior products did not end up dominating the marketplace. An established company with deep pockets can on occasion tolerate an unsuccessful product, although the company’s stockholders might beg the differ; however, for a startup company the success of the initial product is likely to be a life or death event. Ground-breaking technology is a start, but unless it can be productized into a solution that solves actual customer problems, the likelihood of success is minimal. The job of taking this new technology and effectively converting into a product that can be sold to consumers usually falls to a seasoned marketing executive. The problem is, finding one who is able to flourish and succeed in a startup environment is quite difficult, especially since most marketing executives are used to outsized budgets that tend to be available in large corporations. Good thing then that the Caltech Industrial Relations Center together in collaboration with Chris Halliwell have recently started the Technology Marketing Center, or TMC for short. The TMC website is easy on the eyes and has several useful resources including blogs, case studies, and executive interviews which are presented in audio format.

One of the latest interviews is titled: What VCs Want in a Marketing Executive with Charles Beeler and Patty Burke. Charles Beeler and Patty Burke are both associated with El Dorado Ventures, a venture capital firm that provides early-stage funding for technology companies, and present some useful information with regard to hiring a marketing executive for a startup. Topics that are discussed during the interview include: marketing differences between established and startup companies, interview tips for hiring marketing executives, the voice of the consumer process, common marketing issues, marketing tools, and common mistakes. The Q&A session is a little bit too short in my opinion but overall the interview provides some very interesting insight. There are several upcoming interviews that might be of interest as well, including one titled: Creating Market Leadership in China with Patrick O'Doherty from Analog Devices on September 25th at 10 am Pacific Time. All interviews are archived so that they can be replayed later, run about thirty minutes, and are freely available to the public – simply put, there is no reason you should be missing out on them.

The Hot Chips Symposium at Stanford’s University has barely kicked off and already we have a major bombshell from Tilera, namely their TILE64 multi-core processor.  We are not talking four or eight cores here but a whopping 64 full-featured identical cores, each with an integrated L1 and L2 cache, a distributed L3 cache, and an integrated non-blocking switch which is utilized to connect to the iMesh on-chip network.  The iMesh network is Tilera’s implementation of the grid architecture concept, with several enhancements of course, and allows the cores to communicate with each other as well as the main memory and the I/O. Since the cores are full-featured, each is capable of running an independent operating system. The general architecture of the TILE64 is shown in the illustration below.

Combined with a portfolio of 40 patents and the architecture described above, Tilera claims to be able to deliver 40X times the performance of the leading Texas Instruments DSP.  The TILE64 comes in several flavors running between 600MHz and 1GHz.  At these frequencies each core dissipates between 170 and 300mW, respectively.  Assuming the latter frequency, the chip would dissipate around 20 Watts without any of the peripheral circuitry or the network overhead. My guess is that the complete chip consumes at least 30 Watts, this however is pure speculation, since no average or maximum power dissipation numbers are available on Tilera’s website. Also missing from the website are the chip dimensions and the manufacturing node that is currently being utilized – two metrics that are of most interest to designers.

As discussed in previous posts, a multi-core chip is nothing without a good development environment that allows the programmer to take advantage of all the resources. Not to be outdone by other startups in the multi-core race, Tilera offers a Multicore Development Environment (MDE) that is based on the open-source Eclipse IDE, an ANSI C compiler, and a full system simulation model.  There are plans for the environment to support C++ soon as well.  In the meantime, the MDE enables developers to for example cluster cores, such that a particular application can obtain enough processing power. Of course, all this processing power and flexibility does not exactly come cheap, starting at $435 in 10K quantities. There are also plans for a 120 core device and a 36 core device, so we will definitely be hearing more from Tilera in the near future.

SPICE simulations are the essential tool for any circuit designer. Without an accurate SPICE simulator a company might as well forget about reasonable yields when the chip finally tapes out. Nevertheless, with the ever increasing device counts and thus netlists, chip designers have had to make a choice between acceptable accuracy and reasonable runtimes. To overcome this tradeoff, circuit designers have been using many tricks to make current designs possible. For example, instead of simulating an entire block, a particular path of interest can be pruned and then simulated. Another trick is to mix and match extracted cells with cells for which parasitic are estimated on the flight. Yet another approach is to utilize fast-spice simulators, which instead of simulating each device and solving the equations associated with it, employ device switching approximations to estimate how the circuit is going to behave. Regardless, not matter how you slice and dice it, accuracy of the simulation is compromised in each case.

But usually, where there is an interesting problem to solve, you can expect a startup to emerge trying to solve it. Case in point, Cupentino, California based Xoomsys Technology. Backed by Benchmark Capital, Morgenthaler Ventures, and Duff Ackerman & Goodrich, and have just finished second round funding which netted the company a nice $8 million, Xoomsys believe they have found a reasonable solution for the circuit designer’s dilemma. As the illustration below shows, Xoomsys proposes to parallelize the simulation onto a cluster of x86 machines.

The approach is quite elegant and is implemented via what the company refers to as Scalable Performance using Enhanced Effective Decoupling, or SPEED for short. In layman’s terms, SPEED takes an existing netlist and parses it into individual and smaller netlists that can then be sent off to multiple systems that run a regular SPICE simulator on each of the netlists in parallel. The breakthrough here is the ability for Xoomsys the parse the initial netlist in such a way as to minimize the communication between the parallel machines while at the same time balancing the load across all the machines. The minimization in communication is accomplished by figuring out which parts of the netlists are mostly decoupled from each other and as such can be simulated individually. Most importantly, Xoomsys guarantees that the final output of the simulation, when all the pieces are combined back together, will be identical to that of a regular SPICE simulation that would have run on the original netlist. As such, what Xoomsys offers is more of an extension that enables a company to utilize their preferred SPICE engine more efficiently.  And while performance numbers are not listed anywhere on the site, the technology itself seems quite promising.