Arteris, SoC Interconnect IP and Tools

The reports reiterating a VC winter for semiconductor startups just keep on coming, the latest one being from Gartner, discussed here. And yet, clever startups keep on beating the odds, by obtaining funding even given all this negative press. The latest of which is Arteris, an EDA startup specializing in providing SoC interconnect IP and tools, based on the company’s Network-on-Chip (NoC) architecture. Founded in 2003, with headquarters in San Jose, CA and an engineering design center in Paris, France, Arteris just completed a strategic investment round that netted the company $9.7 million in funding. The funding round was led by Qualcomm and ARM, who joined an impressive list of investors including Synopsys, DoCoMo Capital, Crescendo Ventures, TVM Capital and Ventech, in making it possible. Arteris’ technology supports ARM’s Advanced Microcontroller Bus Architecture (AMBA) out of the box, but according to the company can be easily extended to support proprietary bus protocols.

The idea for NoC, the company admits, was taken from applicable concepts in the computer network arena and then adapted to IC design. Arteris currently offers three separate tool chains, depending on the design complexity at hand: FlexWay, FlexNoC, and NoC Solution. FlexWay is targeted to enable designers to quickly replace their current Advanced High-Performance Bus (AHB) by offering improved performance, support for heterogeneous interfaces, and a verification engine to verify the interconnects and interface protocol coverage. FlexNoC, as the next step up, offers multi-protocol support, is optimized for high-throughput while minimizing area and power, and also offers a test suite that promises a 100% interconnect coverage along with functional coverage test on the component interfaces. The top of the line tool, NoC Solution, is target at very complex designs and offers additional features such a Quality of Service (QoS) support, and multiple clock and power domain support, just to name a few. It also features a DRAM scheduler that integrates with the NoC architecture as needed. In addition to the verification engine mentioned beforehand, NoC Solution also comes with a NoCcompiler and NoCexplorer which allow designers to quickly capture, configure, and evaluate their bus architectures.

With the number of components that are being integrated onto SoCs increasing constantly, the tools that Arteris offers might indeed become essential. Especially for smaller integration teams that do not have the resources to evaluate and design proprietary bus architectures for their SoCs. I definitely think that Arteris is on the right track by focusing on a specific problem, namely the bus network architecture, an area which is only going to get more complicated in the near future.