ChipCrunch.com

Achieving maximum performance from your design given constraints such as area and power has been name of the game for a while now. Over the last few years we have seen quite a few approaches to this problem: On the one hand, there have been startups that have ventured down the massively parallel architecture route and then wrote sophisticated tools and compilers that mapped software and programs onto those architectures. Companies such as Ambric and Plurality come to mind - the former has since hit the dead pool while the latter has been strongly marching on. On the other hand, there are companies which have approached the problem from a different angle, focusing on reconfigurable silicon that can be optimized for a given program or task. Companies such as Tabula and their programmable spacetime architecture come to mind. Akya, a startup out of Selby, United Kingdom, which has been developing what it refers to as Akya Reconfigurable Technology (ART), definitely falls into the latter camp.

Akya recently introduced ART2 which is a dynamically reconfigurable logic technology primarily aimed at digital processing functions. ART technology can be used for a whole chip or just parts of a chip where it is needed. The major advantage touted by Akya is the flexibility that ART offers, allowing designs to be modified after tape-out without requiring new silicon while at the same time delivering area and power comparable to hard-wired silicon solutions. The basic building block of the ART architecture is a Reconfigurable Processing Matrix (RPM) as shown in the figure below.

The RPM is composed of Processing Elements (PEs) which are connected by a reconfigurable interconnect (RI). The PEs are selected at design time from the supplied ART2 library, which includes many functional blocks for arithmetic and memory operations amongst others. The Sequencer element is responsible for running a program which defines which operations are performed by the individual PEs and which registers are loaded. The datapath in the RPM can be re-configured each clock cycle. Several RPMs can then be connected together at a higher level via a token ring network to implement the desired functionality, which in turn is controlled via a master controller. Akya splits the design process into two phases: datapath design and control design. The dynamic datapath is developed using the ART Architecture Definition Language (AAD), which is consumed by the ART Architecture Compiler (ARTAC) to generate fully synthesisable Verilog and SystemC collateral. The control functionality is implemented via code using the ART Assembly Language (AAL), which is utilized by the ART Assembler (ARTASM) to generate a bit-stream to be loaded into the device at power-on. If nothing else, Akya has definitely furnished us with plenty of acronyms! The design tools currently support the Artisan libraries down to TSMC 90nm node, as well as the Altera Stratix II FPGA.

As mentioned beforehand, the biggest benefit of the ART2 technology seems to be flexibility. For example, the control firmware can be modified to support slight product variations with the same silicon or it can be updated to fix a few bugs in the field. It could also come in handy when evolving standards get updated and equipment in the field needs to be modified accordingly. Another interesting application is the possibility of combining several low volume devices into one product thus amortizing the development and production costs across these products. It will be interesting to see if Akya's technology finds a home in a few designs in the marketplace.  ART2 definitely looks interesting, but interesting alone does not pay the bills. On that note, if you are absolutelly convinced that the company is on to something and you want to put your money where your mouth is, privately held Akya is actively seeking investors so ping them if so inclined.