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Some conferences are exciting, and others are less so; this year’s ISSCC fell somewhere in-between. The plenary sessions was more interesting than usual, with Jeff Hawkins’s presentation regarding the question as to why computers can’t be more brain like, going over very well with the attendees. If you have not read Jeff’s book titled On Intelligence, you ought to give it a look. His theory regarding hierarchical temporal memory is very interesting and just might inspire people to come up with new approaches to computing in the future.

On the technical side of things, this year’s memory forum focused on embedded memories. For example, engineers from TI do not think that embedded memories such as eDRAM make sense for mobile processors at the moment since capacity wise the cross-over point for eDRAM to become cost-efficient is beyond what mobile processors require at present. On the other hand, given IBM’s need for large caches on some of their processors, it should be of no surprise that they were significantly more upbeat on embedded memory technology. The most interesting slides from a pure technical perspective though were presented by Hiroyuki Yamauchi from the Fukuoka Institute of Technology, in which he depicted SRAM design and scaling limitations in a myriad of graphs. He offered enough data to give one a headache but one thing was clear, the regular six transistor (6T) SRAM memory cell won’t scale, even when combined with other circuit tricks. Tom Andre from Freescale also gave a nice presentation regarding MRAM. If you ever need to understand how a write is performed in a Toggle MRAM send him a note requesting his slides.

The microprocessor session was somewhat exciting mainly because Sun made some interesting architectural decisions for their latest SPARC processor, such as sharing instruction/data caches and ALUs between several cores, implementing the scout-thread model and enabling transactional memory support. Tilera’s presentation was a yawn at best, and featured not much in terms of new content regarding their Tile64 processor, other than an explanation of all the networking protocols that the on-chip network supports. Intel’s 2-Billion Transistor chip featured some interesting soft-error-rate (SER) hardened latches and register files. While they are larger than usual cells, they are significantly easier to implement than ECC for example.

One of the more entertaining evening sessions proved to be the fight them or invite them panel discussion regarding private equity. The panel agreed that private equity probably underestimated the volatility of the semiconductor industry and that the two major experiments last year that featured Freescale and FXP, might have scared private equity firms away from semiconductor companies for now. Straying from the main topic, the discussion also revealed some statistics that ought to be a cause for concern. For example, while in 2007 the amount of venture capital raised by startups has been the highest in six years, the amount of funding for semiconductor companies has actually been decreasing over the last few years. The panel of experts did not have a clear opinion as to why this was the case, other than suspecting that VCs might have found more lucrative opportunities. Additional topics discussed during the session included: the United States being overly capitalistic, the implications of the mortgage and housing crisis on the semiconductor economy, and the decrease of Japan’s market share as a semiconductor supplier over the last few decades. As stated before, it was a very entertaining session.

Need some reading material to get you through the next meeting that you have no interest in but are required to attend? Well, in that case you might want to take a look at Semiconductor International’s Top 100 List of features, blog entries, and webcasts on their website based on the number of views throughout 2007. The articles in the list cover a wide range of the semiconductor spectrum ranging from process development, to nanotechnology, and solar cells. The list actually contains only 99 articles from last year, since it seems that one article from '04 made it onto the list by accident; however, if you don’t manage find anything on the list that might be of interest to you, you are either extremely up to date and well read in the semiconductor field, or you have no interest in semiconductors in the first place, in which case you might want to consider a career change.

Back in December I wrote a short post about magnetoresistive random access memory (MRAM), and a few competing technologies, as well as a short mention about Freescale’s current efforts. Given MRAM’s potential it should be of no surprise that Freescale is not the only name in town when it comes to MRAM. Micromem Technologies Inc., a Canadian fabless semiconductor device company based out of Toronto, announced the other week that they have manufactured a foundry grade fully functional MRAM cell, and intend to deliver it packaged for testing later this month. The company is currently proceeding with a test plan for a 64bit MRAM that builds on top of the current MRAM cell. The 64bit MRAM arrays are expected to be available for testing in three to four months. The currently produced MRAM cell is implemented in a Gallium Arsenide process, but the company intends to migrate its technology into to Silicon Germanium process as well to satisfy the lower cost, higher density memory market. Performance numbers for Micromem’s MRAM are currently no available, but the company expects to communicate the performance data in early February. Capacity wise Micromem is currently far behind players like Freescale who offer chips with up to 4Mbit capacity, but the company claims that its products are significantly less complex, and will be cheaper and less problem prone than competing products. The reduced complexity stems from the fact that Micromem is not utilizing the magnetic tunnel junction (MTJ) approach selected by many of its competitors, which introduces tunnel barrier and structural complexity, but instead opts for using a Hall Cross-Sensor (HCS) approach, thus the name HCS MRAM. Below is a diagram depicting the HCS device concept taken from the Micromem’s press release describing their successful HCS test. Micromem is initially targeting radiation hard applications, radar systems, satellites and sensors with their technology. Overall the technology seems promising; however, it is hard to make a call without any performance numbers so that it can be compared to other MRAM implementation. And while the company has successfully implemented a single bit, it will be interesting to see how their technology scales to larger arrays, and whether the HCS approach will really yield cheaper and more reliable MRAMs than the MTJ approach.

The other week EETimes.com released several snippets from their annual salary and opinion survey. At first it seems that electrical engineers in the United States do rather well compared to their European and Japanese counterparts, with median earnings of $108k, $61k, and $65k, respectively. Now where it gets a little bit confusing is that the median earnings for American engineers include benefits. What is not exactly clear is what benefits are taken into consideration? Medical, 401k, ESPP, bonuses, or maybe all of the above? It is also not clear what benefits, if any, are included for European and Japanese engineers. Sure engineers in many European countries might earn less money wise, but healthcare and other benefits might be provided by the government instead. Some clarification of these points would be very much appreciated. There are also a few other points of concern. Why is it that the survey had 1,600 respondents from the United States and 1,900 from Japan, but only 164 from Europe? Either someone did not do their job very well, or it has to be concluded that the electrical engineering profession has all but disappeared from the European continent. To be fair, 164 respondents are more than EETimes obtained last year, but the number is still rather pathetically small.

Salaries aside, it is clear the engineers in the United States are highly concerned about foreign competition due to outsourcing and H1-B visa levels, as these were the predominantly cited issues of concern. A more detailed breakdown of the immigration issue can be found over here, where a whopping 37% of American engineers support a limit on the number and time that foreign workers may work in the U.S. Furthermore, a staggering 44% believe that foreign nationals that earned engineering degrees in the U.S. ought to be able to work in the U.S. only for a limited amount of time after graduation. This attitude is absolutely contrary to what many economic scholars suggest as the proper course of action for the U.S. in order to stay competitive with other countries over the next few decades. As discussed in a previous post, the Kauffman Foundation for example recommends a disbanding of the H1-B visa cap altogether. Others have suggested for the U.S. to institute programs that would enable students of advanced degrees to obtain citizenship upon successful completion of these degrees. Clearly, what American engineers believe is best for their career in the engineering field at this point does not align with what many policy makers and economic pundits believe to be best for the country in the long-term. Then again, maybe foreign workers don’t exactly want to stick around in the U.S. anyhow. Plenty of developing countries offer very good opportunities for skilled workers nowadays, and most of them offer significantly more vacation time that gets fully utilized by the workforce – translation: no more feeling bad about taking off two or three weeks at a time.