Micromem, foundry grade Hall Cross Sensor MRAM

Back in December I wrote a short post about magnetoresistive random access memory (MRAM), and a few competing technologies, as well as a short mention about Freescale’s current efforts. Given MRAM’s potential it should be of no surprise that Freescale is not the only name in town when it comes to MRAM. Micromem Technologies Inc., a Canadian fabless semiconductor device company based out of Toronto, announced the other week that they have manufactured a foundry grade fully functional MRAM cell, and intend to deliver it packaged for testing later this month. The company is currently proceeding with a test plan for a 64bit MRAM that builds on top of the current MRAM cell. The 64bit MRAM arrays are expected to be available for testing in three to four months. The currently produced MRAM cell is implemented in a Gallium Arsenide process, but the company intends to migrate its technology into to Silicon Germanium process as well to satisfy the lower cost, higher density memory market. Performance numbers for Micromem’s MRAM are currently no available, but the company expects to communicate the performance data in early February. Capacity wise Micromem is currently far behind players like Freescale who offer chips with up to 4Mbit capacity, but the company claims that its products are significantly less complex, and will be cheaper and less problem prone than competing products. The reduced complexity stems from the fact that Micromem is not utilizing the magnetic tunnel junction (MTJ) approach selected by many of its competitors, which introduces tunnel barrier and structural complexity, but instead opts for using a Hall Cross-Sensor (HCS) approach, thus the name HCS MRAM. Below is a diagram depicting the HCS device concept taken from the Micromem’s press release describing their successful HCS test. Micromem is initially targeting radiation hard applications, radar systems, satellites and sensors with their technology. Overall the technology seems promising; however, it is hard to make a call without any performance numbers so that it can be compared to other MRAM implementation. And while the company has successfully implemented a single bit, it will be interesting to see how their technology scales to larger arrays, and whether the HCS approach will really yield cheaper and more reliable MRAMs than the MTJ approach.