We first encountered Tilera back in '07 when the company made the EETimes emerging startup list. We caught up with the company later that year when they revealed the Tile64 processor. The following year the Global Semiconductor Alliance (GSA) recognized Tilera with the startup to watch award. Over the last couple of years Tilera has definitely not been standing still nor resting on their laurels. In '09 they announced the Tile-Gx family of processors, which features devices that range from a relatively humble 16 cores to a massive 100 cores. These devices also go a step further than the company’s previous efforts in terms of system on a chip (SOC) design integrating 64-bit DDR3 interfaces, plenty of Gigabit-Ethernet (GbE) MAC interfaces and hardware encryption and compression support. A high-level view of the Tile-Gx is shown in the figure below. Tilera expects to start sampling these devices, implemented in 40nm technology, later this year. Further out, in the 2013 timeframe, Tilera expects to offer a 200-core processor version, codenamed Stratton, which will be implemented in 28nm technology.

All this progress has not gone unnoticed and earlier this year the company received an additional $25 million in series-C funding, bringing the total venture capital raised to $64 million. Several new strategic investors joined in this round, including Broadcom, Quanta Computer and NTT Financing. The newly raised capital is to be used to broaden the product portfolio and to expand sales activities. With Quanta as an investor the company also went to town on branching out into the cloud computing space. In June the two companies jointly announced a new Quanta cloud server product that packed a stunning 512 cores into a single 2U form factor server while staying under 400 watts. This particular product featured the TilePro64 processors, however, with the future Tile-Gx and Stratton products, companies could potentially offer 20,000 cores per server rack in 2011, and up to 40,000 cores par rack by 2013, respectively. These are mind numbing numbers indeed; it will be interesting to see how Tilera’s proprietary Dynamic Distribute Cache (DDC) which allows for a fully coherent shared cache across an arbitrary array of tiles (processor + switch), as well as the Intelligent Mesh (iMesh) non-blocking cut-through network will scale with the ever increasing core count. With Tilera’s ambitious roadmap and the recent announcement from startup SeaMico touting a 512 processor Intel Atom based product, the server space has suddenly become very interesting again.

Achieving maximum performance from your design given constraints such as area and power has been name of the game for a while now. Over the last few years we have seen quite a few approaches to this problem: On the one hand, there have been startups that have ventured down the massively parallel architecture route and then wrote sophisticated tools and compilers that mapped software and programs onto those architectures. Companies such as Ambric and Plurality come to mind - the former has since hit the dead pool while the latter has been strongly marching on. On the other hand, there are companies which have approached the problem from a different angle, focusing on reconfigurable silicon that can be optimized for a given program or task. Companies such as Tabula and their programmable spacetime architecture come to mind. Akya, a startup out of Selby, United Kingdom, which has been developing what it refers to as Akya Reconfigurable Technology (ART), definitely falls into the latter camp.

Akya recently introduced ART2 which is a dynamically reconfigurable logic technology primarily aimed at digital processing functions. ART technology can be used for a whole chip or just parts of a chip where it is needed. The major advantage touted by Akya is the flexibility that ART offers, allowing designs to be modified after tape-out without requiring new silicon while at the same time delivering area and power comparable to hard-wired silicon solutions. The basic building block of the ART architecture is a Reconfigurable Processing Matrix (RPM) as shown in the figure below.

The RPM is composed of Processing Elements (PEs) which are connected by a reconfigurable interconnect (RI). The PEs are selected at design time from the supplied ART2 library, which includes many functional blocks for arithmetic and memory operations amongst others. The Sequencer element is responsible for running a program which defines which operations are performed by the individual PEs and which registers are loaded. The datapath in the RPM can be re-configured each clock cycle. Several RPMs can then be connected together at a higher level via a token ring network to implement the desired functionality, which in turn is controlled via a master controller. Akya splits the design process into two phases: datapath design and control design. The dynamic datapath is developed using the ART Architecture Definition Language (AAD), which is consumed by the ART Architecture Compiler (ARTAC) to generate fully synthesisable Verilog and SystemC collateral. The control functionality is implemented via code using the ART Assembly Language (AAL), which is utilized by the ART Assembler (ARTASM) to generate a bit-stream to be loaded into the device at power-on. If nothing else, Akya has definitely furnished us with plenty of acronyms! The design tools currently support the Artisan libraries down to TSMC 90nm node, as well as the Altera Stratix II FPGA.

As mentioned beforehand, the biggest benefit of the ART2 technology seems to be flexibility. For example, the control firmware can be modified to support slight product variations with the same silicon or it can be updated to fix a few bugs in the field. It could also come in handy when evolving standards get updated and equipment in the field needs to be modified accordingly. Another interesting application is the possibility of combining several low volume devices into one product thus amortizing the development and production costs across these products. It will be interesting to see if Akya's technology finds a home in a few designs in the marketplace.  ART2 definitely looks interesting, but interesting alone does not pay the bills. On that note, if you are absolutelly convinced that the company is on to something and you want to put your money where your mouth is, privately held Akya is actively seeking investors so ping them if so inclined.

The other day, courtesy of Matt from door64.com, I had a chance to attend the Global Semiconductor Alliance (GSA) Silicon Series luncheon here in Austin, TX. The luncheon was titled “The Future of Consumer Electronics and the Communication Convergence” and was held at the Barton Creek Resort & Spa. The luncheon consisted of a keynote address which was given by Henry Derovanessian, the Vice President of Set Top Box Engineering at DirectTV, and was titled "Communication Convergence: Emerging Technologies in Mobile Computing and the Connected Home." The key note was then followed by a panel discussion titled "Negotiating the Blurred Lines Between Consumer Electronics, Home Networking and Mobile technology." The panel was moderated by Tom Sanderman, Vice President of Manufacturing Systems and Technology at Globalfoundries. The panelists were Patrick Moorhead, Vice President of Marketing at AMD, Sandeep Shah, Director of Marketing and Applications at Marvell Semiconductor, and finally Dr. Naveed Sherwani, Co-Founder, President & CEO at Open-Silicon.

The key note centered on how DirectTV envisions the future deployment of entertainment media inside the house. The presentation slides are available here. Currently home networks are moving from point to point systems to a single cable solution. The reason is simple: With the explosion of set-top boxes and connected devices, point-to-point networks would require an excessive number of cables, and consumers as well as content providers are not interested in technicians spending hours running new cables. Further down the line, according to Henry, expect all the set-top boxes to converge into a single home server, with all connected devices functioning as content streaming terminals. Once again, the reasons are simple: Consumers want to watch their content anywhere, at any time, and in any format. Consumers do not care that they scheduled a recording in the family room downstairs. If they want to watch it upstairs later or stream it to their mobile devices while relaxing in the hammock outside they ought to be able to do so without any problems. From a semiconductor perspective, the central server will need ever more processing power and larger amounts of memory. Driving factors for which will be the need to transcode all of the content into different formats, newer and more advanced 3D user interfaces, and of course the ever increasing amount of clients on the network. Reliability will also become paramount, since if the central server were to go down vs. a single set-top box, the whole home network would become useless.

Not surprisingly networking technologies are also becoming an essential component of the home networking infrastructure. According to Henry, the most popular of which are HomePNA and MoCA, both of which work over existing RG-59/RG-6 coax cables. With versions 3.1 and 2.0, respectively, both offer theoretical bandwidth in excess of 200Mbps. There is also the HomePlug Powerline Alliance which offers bandwidth of up to 200Mbps. Henry also sees potential for WiFi and other wireless technologies, particular with the use of MiMO and beam shaping techniques, although he was cautious to point out that video reliability was still unproven.  He concluded his talk with a brief discussion of the RVU Alliance which is a consortium of companies promoting the user of Remote User Interfaces (RUI) for television or entertainment. One interesting question asked by the audience was whether the future DirectTV server would allow for user content uploads, to which the somewhat surprising answer was that no such possibilities were being examined at this point. Rather, Henry suggested that since the user was likely to have a home PC connected to the same network anyhow, he or she might as well pull it from there. Personally I don’t think that is a very elegant solution, but it might be a direct result of the fact the Henry also does not see any kind of merger of DirectTV and 3rd party internet content, since the business focus is for the customer to view DirectTV programming and not other sources.

The panel was more or less an open discussion questions for the panel varied widely. As expected, given the fact that ARM based processors having been moving up in the performance space while x86 solutions have been pushing into the low-power space, one of the questions centered on x86 vs. ARM architecture. Patrick declined to pick a particular favorite, instead pointing out that conceptually anything can be accomplished with either architecture, and neither is best for all. According to Patrick, the battle lines for the next 5 years have been drawn in the mobile space and as such a lot will depend on the execution. Sandeep pointed out that the world won’t be getting rid of home PCs any time soon, and as such the bread and butter business for the x86 architecture is not at risk. Nevertheless, he thinks that ARM will be keeping the x86 camps up at night. In the ARM space he thinks it will be interesting to watch the development between companies that have only a product license vs. those that have an architectural license. Naveed suggested that the availability of the RTL is a significant advantage for ARM. However, he also pointed out that should x86 RTL become widely available it would be a huge game changer, particularly since companies would be able to utilize decades of x86 research.

Another question that was posed was concerned with the recent emergence of new form factors in the market place. Patrick pointed out that while there might be a myriad of form factors emerging, he has been hearing about the demise of the desktop for 15 years, and so far it simply has not happened. As such new form factors are not a threat to existing form factors. Further, he pointed out that mobile is not always best, and that there will always be a need for central hubs, for such tasks as data backup for example. He pointed out that currently only about 10% of people backup data on a regular basis, and as people learn the hard lesson of losing digital data, which is even easier to do with mobile devices, the demand for central data / backup hubs is likely to increase. Sandeep chimed in and stated that what we are witnessing is a lot of experimentation in the form factor space; however, he does not expect most of these to last. Rather in the future he expects a lot of merging of functionality and thus fewer unique form factors. Consequently, the questioned came up as to why the iPad seemed to be succeeding. Naveed suggested that things succeed not because they are sexy, but because they are useful, and conducive to the way people work. Reverting to the previous question, he cautioned that in his opinion it will take quite a bit of time for convergence to happen, and in the near future, unlike Sandeep, he expects an even great variety of form factors to emerge.

On the more technical side, a question was asked about the future of chip packaging. The panel agreed that in the near future we can expect a continuation of top packaging of devices. There was also consensus that there needs to be more dedicated research on trans-silicon vias (TSV), since a solution was urgently needed. Naveed humored the crowd by stating that in the past one spent all the effort designing the chip and packaging was an afterthought. However, these days it sometimes takes longer to develop the packaging rather than the chip. The audience was also interested in the future of battery technology, given that some of the new smartphones are terrible when it comes to battery life. Once again the panel was in agreement, pointing out that rather than looking for new battery technology to save the day, a lot more emphasis has to be put on low power design on the circuit level and the system level. On a related note, Patrick called for a truth in battery life disclosure, stating that these days it was impossible to compare device specifications and get an accurate picture of how long they will operate without actually testing them.

Finally, one of the last topics that was addressed by the panel had to do with the overall semiconductor model, and what the panelists thought ought to change. Naveed insisted that companies in the semiconductor field need to do a much better job in areas of intellectual property (IP) sharing and validation. When I spoke with him briefly after the panel, he mentioned that in his opinion it was not the manufacturing of the design that was causing most startups to run into the trouble, but rather the integration and validation of 3rd party IP, often times forcing companies to develop components from scratch making the costs prohibitive. Sandeep expanded on this, saying that rather than tying up designers with mundane tasks, we need to let innovators innovate. Designers need to be given a good platform on top of which they can develop, much like in the software realm, since it is then that they are most productive. Interestingly, when discussing the foundry business, Naveed pointed out that in actually the exact opposite was happening. To make design easier, a lot of upfront information from the foundries was needed. However, presently walls were going up, rather than down, since foundries have figured out that making masks on a repetitive basis, rather than the actual chips, was also a very lucrative business.

I left out some of the smaller, but not any less important, questions that the panel addressed, but hopefully the recap above gives you somewhat of an idea about what to expect from a GSA luncheon. Overall, I found it to be a very interesting event that was well organized and which was also very conducive to networking. If you find a GSA luncheon coming to your area, it might be well worth the fee to attend.