The term spacetime usually makes one think about physics, relativity, mathematical models, or at the very list some very interesting science fiction stories - Isaac Asimov anyone? But in this case, we are talking about Tabula, a fabless semiconductor startup out of Santa Clara, California developing programmable logic devices. Founded in 2003, the company currently employs 100+ people and has over the last few years filed over 150 patents, of which over 80 have been granted. The company is backed by several top-tier venture capital firms and has raised a total of $74 million in Series C funding alone. The company first appeared on our radar in October of last year when it made the updated EETimes Silicon 60 list; however, few details were available on the actual technology that the company was pursuing. Things changed at the beginning of this month though as the company emerged from stealth mode and announced what it calls breakthrough spacetime programmable logic architecture.

The basic idea behind the spacetime architecture is shown in the figure above. Essentially, the company is exploring time as a third dimension to reconfigure the logic in a given space, hence the name spacetime. In a regular FPGA, or for the matter in most chips, each area performs a specific logic function. Once that particular area is done performing the desired logical operation, the results are routed to the next stage, where additional logic is performed. Consequently, as the number of logic functions increases the chip area has to also increase in order to accommodate the additional logic. One solution to this problem would be to introduce a third vertical dimension by stack logic stages vertically; however, this would require complex manufacturing steps that are still under development. But, as mentioned beforehand, there exists another solution:  execute the first logic function, save the results, reconfigure the same space for the next function, and utilize the previous results as inputs to the new function. Repeat the process as needed to obtain the final output. Tabula refers to each of these function spaces as folds which are shown in the figure above as Folds 0 through 7. The number of folds, and hence reconfigurations available depends on the chip frequency, and can range from 2 at 800 MHz to 8 at 200 MHz. This approach offers a couple of advantages over regular designs: First, the design space it reused for different functions essentially providing a higher logic density and reducing the chip area needed. Second, since the data is stored locally to be reused in the next fold, no clock cycles are wasted routing data around the chip. One cool feature is that different sections of the chip can have different amounts of folds, which allows for fine granularity when optimizing functions. Another cool feature is that a memory cell with just a single read port can now mimic several read ports, where the number of ports is equivalent to the number of folds.

Now how is all this magic performed you might ask, of taking logic function and assigning it to a design space and separating it further into separate folds? This is obviously not a trivial task, and as such Tabula rightly decided to provide a compiler to automatically manage all of the hardware configurations, given a Verilog/VHDL input. Not much information on the compiler itself is currently published, and as such several questions remain unanswered. For example, it would be interesting to see how the compiler handles cases where there are a lot of conditional branches. Can different types of folds be loaded, i.e. different hardware configurations, based on the outcome of the previous fold. Or are the chip sections configured in such as way that only non-conditional logic is partitioned into folds?  How about, how is the synchronization handled between the different section when they run at different frequencies and have different numbers of folds? Finally, any information pertaining to power consumption is currently not being published, but is definitely of interest considering the number of configurations that happen on the chip any given cycle.  Nevertheless, the technology is exciting and it will be interesting to see what products the company announces in the near future.

There is nothing more interesting than competing technologies pursuing the same end product or application. In the blue corner, founded in 1985 and weighting in at close to 70 patents, please welcome the heavy-weight Anadigics from the GaAs camp. In the opposite red corner, please welcome the feather-weight challengers Black Sand Technologies and VT Silicon from the CMOS camp. All right, the above might be somewhat playful and exaggerated, but this does not mean that a real fight pitting Gallium Arsenide (GaAs) Power Amplifiers (PAs) vs. CMOS based PAs is not shaping up. Take for example the recent column over at EETimes titled "CMOS is the wrong technology for 3G handset PAs ," in which Mario Rivas, the president and CEO of Anadigics Inc., comes out swinging. His claims, paraphrased here for conciseness sake, are as follows: Today’s CMOS amplifiers are not capable of delivering sufficient linear output power to consistently overcome obstacles such as walls, ceilings and trees. Further, GaAs PAs can achieve close to 45 percent efficiency, implying that they are more efficient than CMOS based PAs. GaAs based PAs are more rugged and can deal better with changing environments conditions. And finally, GaAs technology has matured and issues are well understood, resulting in shorter design cycle times as opposed to new and emerging CMOS based implementations. Mario does concede that at some point CMOS based amplifiers might play a role, but not in the near term and not for 3G/4G applications.

Now contrast his claims to those made by the CMOS camp. For example, Black Sand Technologies proudly claims in their most recent press release, which discusses their acquisition of CMOS PA intellectual property from Silicon Laboratories, that replacing GaAs PAs with CMOS based ones improves manufacturing yield, performance, cost, battery life, and call quality. Pretty much countering all the claims made in favor of GaAs by Mario above. Add to this claims from VT Silicon, a startup pursuing silicon based PAs based on Silicon-Germanium (SiGe), of highly linear performance and once again lower production cost.  Add into the mix integrated control circuitry that allows for real-time performance adjustment and power management for the PAs, and ladies and gentlemen we have a fight on our hands! I will be the first one to admit that power amplifiers are absolutely not my forte but this does not preclude me from asking the following: Is Anadigics trying to protect their turf by touting the superiority of the GaAs solutions? Or, being a long time player in the PA space, are they simply utilizing their vast experience and knowledge and pointing out some of the limitations of the current CMOS based solutions. Conversely, are these startups overly optimistic in order to build hype and a market for their products? Will they be remembered as large on promises and short on delivery?  Time will tell, but regardless it will be an interesting conflict to watch as it evolves.

You have a great idea for a semiconductor startup, you have written your business plan, reviewed it a million times, you’ve assembled your team, and everything is ready to go, all that is needed is this annoying thing called money. Who do you approach? If you are well off or have wealthy relatives that trust you at least to some degree, this might not be an issue. Similarly, if you have good connections in the venture capital community be it on the local or national level, you will be fine most likely as well. But for the rest of us, at least knowing which venture capital firms are willing to invest money into semiconductor startups, in this rather tough funding environment, might be at least somewhat beneficial. Thankfully, the guys at TechCrunch Trends recently published their VC Leaderboard: Top 25 Most Active Dealmakers of 2009 article. Their analysis focused mostly on the number of deals, total funding and the mean for each firm. But being the great guys they are, they also provided a download link for their spreadsheet with all the juicy details for the top 100 venture capital firms. If you’re feeling motivated head on over and download it and start digging, otherwise relax as we examine the date from the semiconductor startup point of view.

First, some general statistics regarding the overall funding for semiconductor startups: In 2009 of the top 100 firms, 47 participated in at least one round of funding relating to semiconductors. There were a total of 78 investments in the semiconductor space which totaled $1.16 Billion. The number of investments paled in comparison to other categories such as bio-tech, consumer web, and software, each of which had upwards of 200 investments, placing semiconductors in 8th place of the possible 15 categories used by TechCrunch, excluding the “other” category. When sorted by the total amount of funding received, semiconductor startups move up to 6th, behind bio-tech, consumer-web, software, clean-tech, and enterprise. When analyzed by the average amount of funding per round, semiconductor startups move up all the way to number 3, behind bio-tech and clean-tech. A few observations can be drawn from this. First, while semiconductors and clean-tech had about the same amount of funding rounds, clean-tech netted almost 36 percent more in funding, showing that investors are currently willing to commit more money to clean-tech startups than semiconductors. Second, while clean-tech was all the rage in the media over the last year or so, the investment dollars are still betting on bio-tech companies: Bio-tech ranked first in total funding rounds, total funding, and average funding per round – it is hard to argue with numbers like these. On the positive side for semis, it shows that if you do manage to make it onto the VC radar, you can still count on raising quite a bit of funding per round.

When looking purely at frequency of semiconductor investments, the top VC firm was DCM with 5 investments, followed by Morgenthaler Ventures, DAG Ventures, and Intel Capital with 4 investments each. When ranked by the total amount of investment, the top 5 firms were DCM, Lightspeed Venture Partners, Morgenthaler Ventures, DAG Ventures, and Bessemer Venture Partners. Interestingly, out of all these firms, only Intel Capital was in the top 10 firms when ranked by overall total deal activity and amount of investment. As we mentioned beforehand, there were a total of 78 investments during 2009, however, only 41 unique semiconductor startups received funding. The companies with the highest number of investments were OneChip Photonics, Kovio, and Amalfi Semiconductor with 6, 5 and 4 respectively. They were followed by Unity Semiconductor, Advanced Inquiry Systems, Aquantina, Pixtronix, Direct2Silicon, and Enpirion with 3 each. A lot of investments are not necessarily a good thing. On the one hand, it might indicated that there are plenty of investors eager to throw a lot of money at the company expecting an outstanding return, conversely it might indicate that the company is burning through cash quickly and needs to repeatedly raise money just to stay float or that initial investors are throwing “good money after bad” with the hope of protecting some of the initial investment. Sorted by total amount of funding received, the list of the top 5 companies is as follows: Aquantia, OneChip Photonics, Kovio, Amalif Semiconductor and P.A. Semi. We wrote about Kovio in August and were quite optimistic about the possibilities for the company’s printed silicon, thus them raising a lot of money is not a big surprise. What is rather puzzling is the fact that P. A. Semi made it onto the list. The company was acquired by Apple in 2008 as such this seems somewhat unlikely. Regardless, big thanks go out to the TechCrunch guys for putting all this data together and making it available, allowing us to get a better idea of the semiconductor startup investment climate.